Simple baseband synchronisation scheme for tamed frequencymodulation

A novel carrier and clock synchronisation scheme for tamed frequency modulation is presented. It requires one complex sample per bit, like the digital Costas loop for offset in-phase and quadrature modulations, and is based on processing baseband samples of the phase of the received signal. The performance of the synchroniser is assessed by S-curves and simulated acquisition trajectories     

Decoder-assisted frame synchronisation for turbo-coded systems

An improved frame synchronisation methodology is proposed for turbo-decoded packets using a list synchronisation technique, where a simple synchroniser generates a list of most probable packet starting positions and the following synchroniser makes a refined decision. The second synchroniser is decoder-assisted, accepting soft-decision feedback from the decoder. The performance of the scheme is evaluated via simulation     

基于数字锁相技术的视频同步显示

提出了一种新型实用的基于数字锁相技术的视频同步显示方案,该方案通过采用改进的导前-滞后型数字锁相的方法来调整时钟占空比得到同步的视频输出,并完成了在FPGA平台上的硬件实现.     

All-optical frame synchronisation recovery

All-optical frame synchronisation recovery is demonstrated experimentally. A frame encoded input data signal forces a fibre laser to modelock. The fixed header is copied onto the laser output, whereas in the payload area the clock is recovered. The authors propose to use this frame synchronisation signal in an all-optical demultiplexer that unambiguously identifies each individual channel     

Shannon定理在数字锁相环中的应用

传统的数字锁相环（ＤＰＬＬ）多采用吞脉冲的方法来实现ＤＣＯ,此方法要求工作频率远高于ＤＰＬＬ的输出频率。采用Ｓｈａｎｎｏｎ定理并结合延时抽头技术设计的ＤＰＬＬ,可使ＤＰＬＬ的输出频率接近工作频率。如采用２０ＭＨＺ的主时钟可以产生１６．３８４ＭＨＺ、１２．３５２ＭＨＺ甚至１９．４４ＭＨＺ的频率信号,且能获得较高的频率精度度。同时,本例采用了自适应误差补偿技术,可补偿工艺偏差,同时也可实时补偿由于温度     

原子钟两级驾驭算法及在建立GNSS时间基准中的应用

本文提出了一种原子钟驾驭算法,方法是使用等价于Kalman滤波器加延迟器的数字锁相环（DPLL）。本文完整地推导了DPLL的闭环系统传递函数和闭环误差传递函数,给出了其实现结构,和每次的对于被驾驭原子钟的调整量,并给出了使DPLL输出信号的频率稳定度最优的参数选取方法。在此基础上,提出了使用两个这样的DPLL级联起来的二级驾驭算法。理论分析和仿真实验都表明：该算法相比传统原子钟驾驭算法,参数选取更容易,可以保证输出信号的频率稳定度最优;并保证输出信号与第一级的参考输入保持时间同步。该两级驾驭算法可以应用于设计锁相振荡器,即先用铯钟驾驭氢钟,然后再驾驭数控振荡器（NCO）;也可以应用于建立 GNSS 时间基准,即先用 UTC （BSNC）驾驭产生BDT,然后再用BDT驾驭主控站主钟来产生BDT（MC）。     

基于FPGA的数字锁相环实现与性能分析

在数字通信系统中,对传输数据的位同步信号提取非常重要.在基于FPGA的数字系统中,通常是设计一个数字锁相环(DPLL)来解决这些问题.文章设计一种新的利用bang-bang鉴相器实现的DPLL,bang-bang鉴相器能直接从接收数据流中提取位时钟信号,且在减少抖动、侪频、时钟恢复和数据同步有很好的优越性.分析了,整个数字锁相环在无高斯白噪声环境下的性能,最后给出了整个锁相环的波形仿真.     

一种采用新的相频检测技术的CMOS数字锁相环

提出了一种新型的数字锁相环 (DPLL) ,它的相频检测器采用全新的设计方法 ,与传统电荷泵锁相环相比 ,具有快速锁定、低抖动、低功耗、频率范围宽、且能消除相位“死区”的优点。锁相环在 1.8V外加电源电压时 ,工作在 6 0～ 6 0 0MHz宽的频率范围内 ,最大功耗为 3.5mW。采用分数分频技术 ,具有较小的输出频率间隔 ,并利用Σ Δ调制改善相位噪声性能。设计采用 0 .18μm ,5层金属布线工艺。峰 峰相位抖动小于输出信号周期(Tout)的 0 .5 % ,锁相环的锁定时间小于参考频率预分频后信号周期 (Tpre)的 15 0倍。     

基于FPGA的DDS＋DPLL跳频信号源设计

针对跳频通信系统有固有噪声的特点,结合DDS＋DPLL高分辨率、高频率捷变速度的优点,并采用Altera公司的Quartus-Ⅱ_10.1软件进行设计综合,提出了一种新型的跳频信号源。结果表明,该设计中DPLL时钟可达到120MHz,性能较高,而仅使用了30个LUT和18个触发器,占用资源很少。     

一种具有自校准功能的CMOS分数数字锁相环

提出了一种数字锁相环(DPLL),它的相频检测器采用全新的设计方法和自校准技术,具有工作频率范围宽,抖动低,快速锁定的优点.锁相环在1.8V外加电源电压时,工作在60～600MHz的频率范围内.采用分数分频技术,加速锁定过程并具有较小的输出频率间隔,利用∑-Δ调制改善相位噪声性能.设计在SMIC 0.18μm,1.8V,1P6M标准CMOS工艺上实现,峰-峰相位抖动小于输出信号周期的0.8%,锁相环的锁定时间小于参考频率预分频后信号周期的150倍.     

GPS驯服中无偏滑动平均滤波算法的研究

 分析已有GPS驯服中滤波算法的特点,提出了基于GPS的实时频率误差处理及状态估计的无偏滑动平均滤波算法.该方法继承了普通滑动滤波算法低噪声特点,且用线性回归估计补偿了普通滑动滤波算法的偏差,利用该方法滤除频率测量误差中的频率偏差和多通道GPS接收机秒信号(GPS1PPS)的锯齿误差,并预报晶振状态.MATLAB仿真和实际测试结果都证明了无偏滑动滤波算法比普通滑动滤波有效,提高了晶振频率的长期稳定度和准确度,实际系统中恒温晶振OXCO-131的长期频率稳定度的Allan方差提高了约三个数量级,达到3.5E-12/d.     

Metastability reduction by aperture transformation

A methodology is proposed, which involves the use of an aperture transformer comprising a new controlled clock circuit. For reducing overall metastability by first transforming unsafe edge arrival times into metastability of the control signals. A large reduction in metastability has been demonstrated by the development of a new bit synchroniser built using the methodology     

基于双边沿触发计数器的低功耗全数字锁相环的设计

提出了一种低功耗、快速锁定全数字锁相环的设计方法。该文从消除因时钟信号冗余跳变而产生的无效功耗的要求出发,阐述了双边沿触发计数器的设计思想,提出了用双边沿触发计数器替代传统数字序列滤波器中的单边沿触发计数器的锁相环设计方案,以从降低时钟工作频率、减小工作电压和抑制冗余电路的开关活动性等方面降低系统的功耗;同时在环路中采用自动变模控制技术,以加快环路的锁定速度,减少相位抖动。最后采用EDA技术进行了该全数字锁相环的设计与实现,理论分析和实验结果表明其低功耗性、快速锁定性均有明显改善。     

Dual-loop DLL-based clock synchroniser

A clock synchronisation scheme based on a newly proposed dual-loop delay locked loop (DLL) is presented. The proposed scheme incorporates analogue and digital DLLs to align phases of two different frequency clocks. Simulation results show that the internal clock can be synchronised to the reference clock by tracking the dual feedback loop. The whole circuit design was implemented using 0.35 μm CMOS technology. Power dissipation is ~42 mW with a single 3.3 V supply     

Novel design of travelling-wave FET

In the letter we propose a novel travelling-wave FET, in which an additional image gate is placed beside the drain of the FET as a phase velocity synchroniser. Small-signal analysis is given in the light of coupled wave theory and shows that the device is capable of high gain and wide bandwidth amplification. The easy adjustment of phase synchronisation and compability of the conventional FET fabrication technique make it promising for high-frequency distributed amplification.     

Narrow bandwidth polarisation scrambler using delay-coupled binary phase pulse for super-dense WDM networks

A novel polarisation scrambler that offers narrow spectrum bandwidth due to the use of delayed binary phase pulses coupled with orthogonal polarisation is proposed. The performance of the proposed scrambler is confirmed analytically and experimentally for carrier-distributed super-dense WDM (SD-WDM) networks without network clock synchronisation.     

基于FPGA的积分型数字锁相环的设计与实现

位同步时钟信号的提取是通信系统中的关键部分,应用数字锁相环可以准确地从输入码流中提取出位同步信号.本文简要介绍了数字锁相环的基本原理,在详细介绍了积分型超前—滞后数字锁相环的工作原理的基础上,利用VHDL语言对该系统进行了设计,给出了数字锁相环路主要模块的设计方法及仿真结果,得到了该系统的顶层电路,其中重点分析了积分型数字鉴相器的原理,给出了设计过程；并根据系统的参数进行了性能分析,最后给出了整个系统的功能仿真结果.具有一定的工程实用价值.     

Theory of mutually synchronised systems

A method of synchronisation in time-division communication systems is proposed which establishes synchronism by mutual interaction of all the clock sources in the system. Analysis of the static and dynamic behaviour of the system frequency is given, showing the feasibility of mutual synchronisation.     

A direct sequence spread spectrum code acquisition circuit for wireless sensor networks

Narrow band (NB), spread spectrum (SS), and ultra wide band (UWB) are three physical layer bandwidth types used in wireless sensor networks (WSN). SS and UWB technologies have many advantages over NB, which make them preferable for WSN. Synchronisation of different nodes in a WSN is an important task that is necessary to improve cooperation and lifetime of nodes. Code acquisition is the main step of a node’s time synchronisation. In this article, a pseudo noise code generator and a code acquisition circuit are proposed, designed and tested using direct sequence SS technique. To investigate the properties of the designed circuits, simulations are carried out via Xilinx Foundation Series software in the real mode. The results demonstrate excellent performance of the proposed algorithms and circuits in all realistic conditions. The code acquisition circuit proposed an adaptive testing window for single dwell serial search method. The code acquisition circuit is a clock phase free approach, thus the clock coherency step is cancelled. Moreover, clock phase difference between transmitter and receiver nodes does not mostly affect the acquisition and thus synchronisation time.     

Novel PLL-based clock distribution scheme

A technique for minimising clock skew in VLSI chips and multichip modules is proposed. A phase-locked loop is used to tune the delay of the clock interconnects. Negative, zero and positive delays can be achieved. This allows for clock synchronisation between individual modules with locally optimised clock distribution to minimise global clock-skew.<>