一种基于MEMS芯片的新型地面大气电场传感器

该文基于MEMS电场敏感芯片,研制出了一种新型的地面大气电场传感器,解决了现有场磨式电场仪易磨损、功耗大、故障率高等问题。敏感芯片采用SOIMUMPS加工工艺制备,其芯片面积仅为5.5 mm5.5 mm。该文提出了传感器敏感芯片的弱信号检测方法,设计出了满足环境适应性的传感器整体结构方案,并建立了传感器的灵敏度分析模型。对电场传感器进行测试,测量范围为-50 kV/m~50 kV/m,总不确定度为0.67%,分辨力达到10 V/m,功耗仅为0.62 W。外场试验结果表明,MEMS地面大气电场传感器在晴天和雷暴天的电场探测结果,与Campbell公司场磨式电场仪探测结果都有较好的一致性,说明该传感器能满足预测雷暴要求,实现雷电监测和预警功能。     

基于磁流体磁体积效应的磁场与温度双参量传感器

为了实现磁场与温度的同时测量,提出并制作了一种基于磁流体(magnetic fluid, MF)磁体积效应的法布里-珀罗(Fabry-Perot, FP)腔与光纤布拉格光栅(fiber Bragg grating, FBG)级联的复合传感结构。注入空芯光纤(hollow-core fiber, HF)的MF液面与单模光纤端面形成的FP腔同时对磁场和温度敏感,与之级联的FBG只对温度敏感。通过同时监测FP腔特征峰与FBG布拉格反射峰的波长漂移,利用传感器磁场与温度敏感系数矩阵,同时获取温度与磁场信息。实验成功制备了初始腔长为56.1μm的FBG-FP温度磁场双参量传感器,磁场与温度灵敏度分别达到了16.21 pm/Oe和9.96 pm/℃,具有体积微小、结构简单、成本低等特点。该传感器可解决常规光纤磁场传感器的磁场-温度交叉敏感问题。     

高灵敏度Si基纤毛式MEMS湍流传感器

为了满足湍流探测高灵敏度、高分辨率的要求,提出了一种新型纤毛微电子机械系统(MEMS)湍流传感器。基于MEMS技术制作了硅十字梁敏感受力结构,通过橡胶探头的受力振动传递水中的湍流信号,凭借传感器头部的导流罩来保证传感器的高分辨率探测。对MEMS湍流传感器进行理论和仿真分析,其一阶共振频率达到481.04 Hz。经过海洋环境模拟机测试实验,结果显示其在50 MPa压力下保持了完好的结构和良好的性能,验证了其水下的可靠性。在湍流实验平台进行测试,通过比较标定法得出其灵敏度为1.92×10^-4 V·m·s^2/kg,满足海洋湍流测试要求。     

基于柱矢量模式的光纤迈克尔逊传感特性研究

基于涡旋光纤(vortex fiber,VF) 激发的柱矢量模式(cylindrical vector modes,CVMs) 设计了迈克尔逊干涉仪传感器,并对轴向应变、温度和折射率传感特性进行了理论研究和实验验证。 通过对VF施加一个微弯长周期光栅(microbend long period gratings,MLPG),激发一阶CVMs(TE₀₁、HE₂₁和TM₀₁);在VF尾端加反射镜,反射后纤芯中的基本模式HE₁₁与环芯中的CVMs产生干涉,构成了迈克尔逊干涉仪。实验测得对应于柱矢量模式TM₀₁、HE₂₁和TE₀₁的应变灵敏 度分别为-1.1 nm/mε、-1.1 nm/mε和-2.1 nm/mε,温度灵敏度分别为9.3 pm /℃,3.4 pm /℃和-2.4 pm /℃,而折射率不敏感。该传感器结构简单,且TE₀₁模式具有最高应变灵敏度和最低温度灵敏度,可作为折射率不敏感的、温度交叉灵敏度低的理想无补偿应变传感器,是智能型工程结构中下一代传感器的理想选择。     

基于锆钛酸铅的低电压驱动MEMS电场传感器研究

该文提出一种基于锆钛酸铅(PZT)的低电压驱动微机电系统(MEMS)电场传感器。该传感器基于电荷感应原理,其敏感单元由固定电极和可动电极构成。固定电极与可动电极均为感应电极,同时两者又是屏蔽电极。在PZT压电材料的驱动下,可动电极产生垂直于敏感芯片基底的振动并且与固定电极形成交互屏蔽,当存在待测电场时,分别在可动电极和固定电极上产生相位差为180°的感应电流信号。该文进行了传感器的设计和有限元仿真,提出敏感微结构的加工工艺流程,突破了基于PZT压电材料的可动电极MEMS工艺兼容制备技术,完成了敏感芯片制备,对传感器进行了性能测试。该传感器具有工作电压低的突出优点。实验测试表明,在0～50 kV/m电场强度范围内,采用1 V交流驱动电压,电场传感器的灵敏度为0.292 mV/(kV/m),线性度为2.89%。     

基于压力分布测试的电容式压力传感器北大核心

针对0-0.3 N压力的大小与分布测试,设计了一款电容式压力传感器。通过ANSYS仿真与Matlab数据分析,确定传感器单个敏感单元半径为80μm,腔高0.5μm,膜厚2.5μm。阵元内敏感单元呈行列排布。设计工艺加工流程与版图,并进行干法刻蚀、减薄和键合等关键工艺加工。使用阻抗分析仪和压力计搭建测试平台,结果显示加工得到的压力传感器初始电容平均值为38.03 pF,阵列内电容一致性良好,灵敏度为9.5 pF/N,线性度良好,连接配套数据处理电路可实现压力分布测试。初步满足在小量程压力条件下测试要求,验证了该传感器结构的可靠性,为制备小量程压力传感器奠定基础。     

MEMS电容式超声传感器设计

在传统的电容式超声传感器(CMUT)制造过程中,用低压化学气相淀积技术形成的氮化硅薄膜残余应力大且机械性能难以预知。为此,设计了一种基于阳极键合技术的CMUT,传感器薄膜和空腔分别定义在均匀性好、残余应力低的SOI片和玻璃片上。建立了一个简化的分析模型对该结构进行机械性能分析,采用有限元分析软件ANSYS仿真验证该所建立的分析模型并预估传感器的性能。利用ANSYS静电 结构耦合仿真给出了塌陷电压。介绍了敏感单元的工艺流程。所设计的传感器频率为1.48 MHz,灵敏度为0.24 fF/Pa,塌陷电压为70 V,量程为48 kPa。     

用于流速测量的微型力传感器的研制

设计并仿真了一种压阻式六自由度力传感器及其测量电桥,采用微电子机械系统(MEMS)加工技术制备了以单晶硅为结构材料的六自由度力传感器,完成了传感器芯片的封帽式封装。压阻式六自由度力传感器的尺寸为5 mm×5 mm×3 mm,由传感器芯片、探测柱和封装外壳组成。基于流体的绕流阻力效应,完成了压阻式六自由度力传感器水流流速检测实验。实验证明,该传感器的量程为0～0.55 m/s,可以灵敏检测到低速水流的波动性变化,并且传感器在水流速度为0.45～0.55 m/s的测量范围内灵敏度较高。利用单晶硅材料易于小型化、滞后极小的特点,该六自由度力传感器响应快、环境适应性强、可批量制造。     

一种新型岛膜压力传感器的研究与设计北大核心

设计了一种量程为180 kPa的新型岛膜结构MEMS压阻式压力传感器,通过ANSYS仿真软件,得出了在岛宽为500μm、岛厚为40μm、梁宽为200μm、敏感薄膜厚为15μm的情况下,该结构具有较好的线性度及灵敏度。提出了一种基于两层SOI硅-硅直接键合的工艺加工方法,能够精确控制敏感薄膜及岛的厚度,并且全硅结构器件能够避免键合残余应力,大大提高器件性能。采用了双惠斯登电桥电路减小传感器输出的温漂效应,并设计了该电路的压敏电阻连接图。最后对该压力传感器进行了测试,结果表明,其非线性为0.64%,精度为0.74%,满足现代工业应用要求。     

基于PZT压电薄膜的压力传感器工艺研究

选用敏感材料锆钛酸铅(PZT),优化微机电系统(MEMS)微加工工艺,制作了硅基PZT压电薄膜叉指式电极结构的MEMS压力传感器。在基体Au/Ti/LNO/SiO_2/Si<100>上,采用溶胶-凝胶(Sol-Gel)法,在650℃高温下采用分层退火的方式进行退火,得到厚1.2μm的PZT压电薄膜。薄膜表面均匀,无裂纹。利用光刻工艺和低压溅射工艺得到平行叉指电极。制作完成PZT压电薄膜结构的微压力传感器,在弹性薄膜上施加压力,其电压输出性能较好,说明基于压电薄膜的叉指电极结构可行,为基于纳米纤维结构的微压力传感器的制作奠定了理论基础。     

CMOS图像传感器IBIS5-B-1300的驱动时序设计

介绍Cypress公司的图像传感器IBIS5-B-1300,分析其特性和工作原理,并对其两种快门方式进行了比较。在此基础上设计它所需要的时序控制电路。选用Xilinx公司的Spartan3系列FPGA芯片XC3S50作为硬件设计平台,对采用不同配置和快门的时序控制电路进行了仿真。实验结果表明,设计的驱动电路能够满足成像器的工作需求。     

全局快门CMOS图像传感器研究进展

全局快门CMOS图像传感器广泛应用于高速运动物体的成像,包括机器视觉、工业测量、航空航天,以及军事应用等领域.介绍了全局快门CMOS图像传感器的主要类型,具体分析了灵敏度、寄生光灵敏度、读出噪声、动态范围和帧频等性能参数的研究进展.最后对国内外有代表性的全局快门CMOS图像传感器产品进行了介绍.     

高分辨率双快门模式CMOS图像传感器控制电路的设计与仿真

主要介绍了一种可用于空间信息获取的高分辨率双快门模式CMOS图像传感器,分析比较了该CMOS图像传感器卷帘式和同步式两种快门模式的工作原理和特点,设计了两种快门模式的时序控制电路并进行了仿真和验证,结果表明了控制电路设计的正确性,并可适用于空间微纳型卫星的成像系统。     

A 1/3-in 270000 pixel CCD image sensor

A 1/3-in interline transfer charge-coupled-device (CCD) image sensor with 270000 pixels has been developed. The effective sensing area of (4.8(H)×3.6(V)) mm² is adopted for the 1/3-in format. This sensor realizes 330 TV lines of color horizontal resolution. In addition, a new on-chip color filter is used, and a minimum object illuminance of 3 1x has been achieved. The electronic shutter was realized by developing the vertical-extraction method, with a wide range of shutter speed from 1/60 to 1/10000 s. Moreover, the use of an embedded photodiode makes it possible to achieve a low dark current. This feature, together with the 5-V drive, gives the sensor additional high performance, including low smear (0.01%)     

CMOS active pixel sensor star tracker with regional electronicshutter

A 64×64 element CMOS active pixel sensor (APS) for star tracker applications is reported. The chip features an innovative regional electronic shutter through the use of an individual pixel reset architecture. Using the regional electronic shutter, each star in the field of view can have its own integration period. This way, simultaneous capture of bright stars with dim stars is accommodated, enabling a large increase in tracker capability. The chip achieves 80 dB dynamic range, 50 e-rms read noise, low dark current, and excellent electronic shutter linearity     

半导体激光器干扰CCD传感器实验研究

为拓展半导体激光器的应用,开展了半导体激光器对可见光CCD传感器的干扰实验研究,得出CCD饱和像素个数与激光输出功率和CCD传感器电子快门时间的对应关系.当电子快门时间分别为t=1/10000 S、t=1/4000 S和t=1/2000 S时,CCD的饱和阈值分别为1W、1W和2.8W."软损伤"的阈值为10W,然而,在激光输出最大功率为22.4W的条件下并没有使CCD损伤.     

Effect of Total Ionizing Dose Damage on 8-Transistor CMOS Star Sensor Performance

Semiconductors - The effects of total ionizing dose (TID) radiation from 60Co gamma-rays on an 8-transistor global shutter exposure complementary metal-oxide semiconductor image sensor (CIS) within...     

Time-Delay-Integration Architectures in CMOS Image Sensors

Difficulty and challenges of implementing time-delay-integration (TDI) functionality in a CMOS technology are studied: synchronization of the samples forming a TDI pixel, adder matrix outside the array, and addition noise. Existing and new TDI sensor architecture concepts with snapshot shutter, rolling shutter, or orthogonal readout are presented. An optimization method is then introduced to inject modulation transfer function and quantum efficiency specification in the architecture definition. Moderate spatial and temporal oversamplings are combined to achieve near charge-coupled device (CCD) class performances, resulting in an acceptable design complexity. Finally, CCD and CMOS dynamic range and signal-to-noise ratio are conceptually compared.     

An Improved Global Shutter Pixel with Extended Output Range and Linearity of Compensation for CMOS Image Sensor

An improved global shutter pixel structure with extended output range and linearity of compensation is proposed for CMOS image sensor. The potential switching of the sample and hold capacitor bottom plate outside the array is used to solve the problem of the serious swing limitation, which will attenuate the dynamic range of the image sensor. The non-linear problem caused by the substrate bias effect in the output process of the pixel source follower is solved by using the mirror FD point negative feedback self-establishment technology outside the array. The approach proposed in this paper has been verified in a global shutter CMOS image sensor with a scale of 1024×1024 pixels. The test results show that the output range is expanded from 0.95V to 2V, and the error introduced by the nonlinearity is sharply reduced from 280mV to 0.3mV. Most importantly, the output range expansion circuit does not increase the additional pixel area and the power consumption. The power consumption of linearity correction circuit is only 23.1μW, accounting for less than 0.01％ of the whole chip power consumption.     

A 9-V/Lux-s 5000-frames/s 512/spl times/512 CMOS sensor

A high-responsivity 9-V/Lux-s high-speed 5000-frames/s (at full 512/spl times/512 resolution) CMOS active pixel sensor (APS) is presented in this paper. The sensor was designed for a 0.35-/spl mu/m 2P3M CMOS sensor process and utilizes a five-transistor pixel to provide a true parallel shutter. Column-parallel analog-to-digital converter (ADC) architecture yields fast readout from pixels and digitization of the data simultaneously with acquiring a new frame. The chip has a two-row SRAM to store data from the ADC and read previous rows of data out of the chip. There are a total of 16 parallel ports operating up to 90 MHz delivering /spl sim/1.3 Gpixel/s or 13 Gb/s of data at the maximum rate. In conclusion, a comparison between two high-speed digital CMOS sensor architectures, which are a column-parallel APS and a digital pixel sensor (DPS), is conducted.