The Physics of Failure of MIS Devices Under Radiation

Unlike the solar cell and the NPN transistor, the MOS device does not sustain a degradation as the principal effect of exposure to nuclear radiation. Instead, the MOS device undergoes a change of operating region, the change being in the nature of a parallel shift of the characteristic curve of the device, produced by the trapping of radiation-excited holes within the 2000-? insulator and the consequent buildup of a fixed bulk space charge in the insulator. Less significant changes under radiation are variations in the shape of the characteristic curve and increased leakage current. These are genuine degradation effects and are closely analogous to the strong effects of ionizing radiation in planar-passivated junction devices such as bipolar transistors, SCRs, diodes, etc. In the latter cases, the devices are acting as MIS devices and hole trapping in the oxide is again responsible for their degradation. A consideration of the case of simple MIS devices under radiation is thus found helpful in elucidating some other important types of failure under radiation of silicon junction devices.     

The silicon-silicon dioxide system

Study of the silicon-silicon dioxide system as a junction between a nearly ideal semiconductor and insulator has aroused both scientific and technological interest. Surface phenomena associated with this system are influenced by contamination and imperfections in the oxide, impurity redistribution in the silicon near the oxide, and finally by additional electronic energy states at the oxide-silicon interface. Over the past few years, the MOS (metal-oxide-semiconductor) approach has been highly developed and is the principal tool for the investigation of silicon surface phenomena. The theory of the ideal MOS capacitor is reviewed followed by a study of its use in the analysis of surface effects. Finally, the three-way relationship of the effect of oxide formation conditions and heat treatment on the properties of the oxidized silicon surface, and the subsequent influence of the properties of this surface on semiconductor device parameters is reviewed.     

Thin-film silicon-on-sapphire deep depletion MOS transistors

This paper describes thin-film MOS transistors in which the entire silicon film forms the conducting channel, not just the surface inversion layer. Single crystal silicon which is epitaxially deposited on sapphire to a thickness of 0.5 to 2.0 microns forms the channel of the field-effect transistor. The oxidations for the channel oxide were done in both steam and dry oxygen ambients resulting in very little oxide charge (0-2 × 10¹¹cm^-2) on both [111] and [100] silicon orientations. No orientation dependence was observed. The absence of an active substrate leads to device characteristics that are significantly different from MOS transistors made on thick silicon. Analysis of the output characteristics and the C-V curve of these devices enables one to study the characteristics of the silicon film and its two surfaces. It is shown that the silicon-sapphire interface region has similar characteristics to the silicon-silicon dioxide interface region in its tendency to support donor sites after heating in hydrogen. To facilitate analysis of the C-V curve, two interesting relations are derived: specifically, the slope of the curve is related to the doping density of the silicon, and the 0.95 level on the normalized curve is shown to be offset approximately one volt from flat-band potential regardless of oxide thickness or doping density, provided these parameters set the normalized flat-band capacitance significantly below 0.95. The use of thin high resistivity p-type films allows one to fabricate p-type enhancement transistors which exhibit a low threshold voltage due to the fact that the silicon surface does not have to be inverted before the channel conducts. Finally, partial-gate deep depletion transistors are examined and it is shown that a substantial increase in drain breakdown voltage may be obtained with thiss geometry.     

Effects of ion-beam mixing on the performance and reliability ofdevices with self-aligned silicide structure

The uniformity of Ti silicide resistance has been greatly improved by using an ion-beam mixing technique. The integrity of both MOS capacitors and p-n junction diodes has been improved. N-channel MOS field-effect transistors fabricated with this technique show better electrical characteristics, less electron trapping in the gate oxide, and better hot-carrier resistance than with devices made without the use of ion-beam mixing     

Total ionizing dose effects in shallow trench isolation oxides

The peaked evolution of leakage current with total ionizing dose observed in transistors in 130 nm generation technologies is studied with field oxide field effect transistors (FOXFETs) that use the shallow trench isolation as gate oxide. The overall radiation response of these structures is determined by the balance between positive charge trapped in the bulk of the oxide and negative charge in defect centers at its interface with the silicon substrate. That these are mostly interface traps and not border traps is demonstrated through dynamic transconductance and variable-frequency charge-pumping measurements. These interface traps, whose formation is only marginally sensitive to the bias polarity across the oxide, have been observed to anneal at temperatures as low as 80 °C. At moderate or low dose rate, the buildup of interface traps more than offsets the increase in field oxide leakage due to oxide-trap charge. Consequences of these observations for circuit reliability are discussed.     

Some observations on charge buildup and release in silicon dioxide irradiated with low energy electrons

The positive charge buildup produced in silicon dioxide by low energy electrons (0 to 30 keV) has been investigated as a function of beam energy and oxide thickness. The induced charge, as evidenced by displacement of capacitance versus voltage plots, was found to be a function of the beam energy dissipated within the oxide in the vicinity of the oxide-silicon interface. The charge induced at a particular fluence level in an oxide of given thickness increases with energy up to some level Emaxbeyond which the charge buildup rate falls off as the energy is increased further. Continued falloff in the buildup rate was observed in several samples irradiated at energies of 200 keV and 1 MeV. Emaxhas been found to correspond to the beam energy which, according to predicted range-energy data, produces maximum energy dissipation per unit path length in the oxide near the silicon interface. Constant temperature annealing of irradiated MOS samples has indicated that the annealed charge is linearly dependent on the logarithm of elapsed time over a finite time interval. This is particularly evident at room temperature where a linear dependence on In (t) has been observed out to 10⁵seconds. Such a time dependence of released charge can result either from thermal activation of trapped carriers from a uniform trap distribution or from thermal emission of recombination electrons over a Schottky barrier from the silicon into the oxide; however, both of these models predict the released charge to be a linear function of absolute temperature. A much stronger temperature dependence has been observed during these experiments.     

Mechanisms of positive gate-bias stress induced instabilities in CMOS transistors

Increase of positive gate oxide charge and interface trap densities has been shown to be responsible for positive gate-bias stress induced instabilities of threshold voltage and gain factor in Al-gate and Si-gate CMOS transistors. The electron tunneling from trivalent-silicon and/or oxygen-vacancy defects into the oxide conduction band has been established as a mechanism of the positive gate oxide charge creation. The creation of interface traps, appearing due to interfacial trivalent silicon atoms, has been related to the reaction between interfacial Si-H or Si-OH groups and the positive gate oxide charge built up close to the oxide-silicon interface.     

Interface states in metal-oxide-semiconductor field-effect transistors

The effect of Co⁶⁰-γ-radiation on MOS field-effect transistors manifests itself as a shift of the characteristics, a decrease in the transconductance and the appearance of long time instabilities.

In this paper the results of an investigation of the instabilities produced by charge exchange associated with states near the oxide-silicon interface are reported. A method for determining, in nearly the whole energy gap, the distribution of energy levels and time constants of interface states is presented. The sensitivity is sufficient to allow an investigation of interface states even in unirradiated transistors.

The measured distribution, P(τ), of the time constants of the slow interface states, τ, is approximately of the form 1/τ and thus explains the appearance of a 1/ƒ noise power spectrum. Interpreting the observed phenomena with a semi-classical tunnelling model leads to the conclusion that the spatial distribution of the slow interface states is fairly constant throughout the first 20 Å from the interface into the oxide layer.     

Direct-current measurements of oxide and interface traps onoxidized silicon

A direct-current current-voltage (DCIV) measurement technique of interface and oxide traps on oxidized silicon is demonstrated. It uses the gate-controlled parasitic bipolar junction transistor of a metal-oxide-silicon field-effect transistor in a p/n junction isolation well to monitor the change of the oxide and interface trap density. The dc base and collector currents are the monitors, hence, this technique is more sensitive and reliable than the traditional ac methods for determination of fundamental kinetic rates and transistor degradation mechanisms, such as charge pumping     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

Radiation resistance of Al2O3MOS devices

Integrated circuits employing MOS devices will play a vital role in tomorrow's civilian and military electronics if their degradation in a radiation environment can be eliminated. One possible approach toward alleviating radiation effects in MOS devices is to use a material with a defect structure that does not allow predominant trapping of either holes or electrons as a gate insulator. This has been done by constructing MOS devices with plasma-grown aluminum oxide. The Al2O3films are formed by first depositing aluminum on freshly cleaned and properly prepared silicon wafers. Subsequently this aluminum is oxidized in an oxygen plasma and device fabrication is then completed. The devices have excellent characteristics and stability, and their fabrication is not restricted by the conditions of the ultra-clean procedures necessary for SiO2-Si devices. Exposure to 1-MeV electron bombardment at various fluence levels and bombardment-bias conditions shows that these structures possess remarkable radiation resistance. Up to a fluence of 1 × 10¹³e/cm², under positive or negative bias, no oxide charge buildup or interface state generation is detectable. Above that fluence, only small shifts are observed. This indicates that an order of magnitude improvement in device hardening can be achieved by the use of this material.     

Nitrogen Plasma Processing of SiO2/4H-SiC Interfaces

A nitrogen plasma annealing process for gate dielectric applications in 4H-SiC metal oxide semiconductor (MOS) technology has been investigated. This process results in substantially greater interfacial N coverage at the SiO₂/4H-SiC interface and lower interface trap densities than the state-of-the-art nitric oxide (NO) annealing process. Despite these exciting results, the field-effect mobility of MOS field-effect transistors (MOSFETs) fabricated by use of this process is very similar to that of NO-annealed MOSFETs. These results emphasize the importance of understanding mobility-limiting mechanisms in addition to charge trapping in next-generation 4H-SiC MOSFETs.     

注F栅介质抗电离辐射损伤机理

对含 F MOS结构的抗电离辐射特性和机理进行了系统研究。其结果表明 :F减少工艺过程引入栅介质的 E’中心缺陷和补偿 Si/ Si O2 界面 Si悬挂键的作用 ,将导致初始氧化物电荷和界面态密度的下降 ;栅 Si O2 中的 F主要以 F离子和 Si- F结键的方式存在 ;含 F栅介质中部分 Si- F键替换 Si- O应力键而使 Si/ Si O2 界面应力得到释放 ,以及用较高键能的 Si- F键替换 Si- H弱键的有益作用是栅介质辐射敏感性降低的根本原因 ;含 F CMOS电路辐射感生漏电流得到抑制的主要原因是场氧介质中氧化物电荷的增长受到了明显抑制。     

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are examined. The radiation tests are performed at ⁶⁰Co sources at the dose rate of 50 rad (Si)/s. The investigation''s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation structure is the main total dose problem. The total ionizing dose (TID) radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is established. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I-V characteristics of 180 nm commercial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.     

MOS 场引晶体管双极理论和实验

提出场引晶体管双极理论.替代已55年久,1952 Shockley发明单极理论.解释近来双栅纳米硅MOS晶体管实验特性--两条电子和两条空穴表面沟道,同时并存.理算晶体管输出特性和转移特性,包括实用硅基及栅氧化层厚度.理算比较最近报道实验,利用硅FinFET,含(金属/硅)和(p/n)结,源和漏接触.实验支持双极理论.建议采用单管,实现CMOS倒相电路和SRAM存储电路.     

MOS场引晶体管双极理论和实验

提出场引晶体管双极理论.替代已55年久,1952 Shockley发明单极理论.解释近来双栅纳米硅MOS晶体管实验特性--两条电子和两条空穴表面沟道,同时并存.理算晶体管输出特性和转移特性,包括实用硅基及栅氧化层厚度.理算比较最近报道实验,利用硅FinFET,含(金属/硅)和(p/n)结,源和漏接触.实验支持双极理论.建议采用单管,实现CMOS倒相电路和SRAM存储电路.     

Bias-temperature stability of nitrided oxides and reoxidized nitrided oxides

It is well known that bias-temperature stressing of MOS devices produces increased interface state densities and insulator fixed charges, thus limiting the high temperature applications of these devices. Nitrided oxides have previously been reported to offer increased resistance to interface state generation and insulator charge buildup in ionizing radiation and room temperature hot electron stress, but under some nitridation conditions are known to suffer from problems which include a low field bias temperature instability. We will report that reoxidized nitrided oxides can offer increased resistance to both bias-temperature stress-induced interface state generation and insulator charge buildup compared with the original oxides.     

Residual damage effects on gate contacts formed on SiC surfaces etched by using the amorphization technique

A trench fabrication process has been proposed and experimentally demonstrated for silicon carbide using the amorphization technique. In the present work, the quality of gates [oxide for metal oxide semiconductor field-effect transistors (MOSFETs) and Schottky barrier contacts for metal semicondcutor field-effect transistors (MESFETs)] fabricated on the etched surfaces are compared with those formed on the as-grown silicon carbide surface. The resistivity and breakdown electric field of the thermal oxide grown on the etched surface was found to be comparable to that of thermal oxide grown on silicon. However, a large concentration of acceptor type interface states (0.5-1 x 10¹³ cm⁻²eV⁻¹) was observed. This results in a large negative interface charge at room temperature and a significant shift in flat band voltage as a function of temperature, which makes the process unsuitable for formation of gates in UMOSFETs. Titanium Schottky contacts formed on the etched surface showed superior reverse current-voltage characteristics and higher breakdown voltages than the Schottky diodes formed on unetched surface with similar doping concentrations. This indicates that the argon implant process for trench formation is suitable for fabrication of gate regions in high voltage vertical MESFETs (or SITs).     

The Effect of the Ionizing Radiation Intensity on the Response of MOS Structures

Semiconductors - The effect of the intensity of ionizing radiation on the volume charge and surface-state density of metal—oxide—semiconductor (MOS) structures with thin gate silicon...     

Comparison of simple models of cylindrical and plane field-effect transistors

The electrical properties of plane field-effect transistors with different assumed impurity-atom distributions in their channel regions, corresponding to either an alloyed- or a diffused-gate p-n junction, are compared with those of the cylindrical type, with a uniform distribution of impurities in the channel. It is shown that the electrical properties of different types of field-effect transistors with the same pinchoff voltage and transconductance are quite similar.