1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

Continuously tunable 1.55-/spl mu/m VCSEL implemented by precisely curved dielectric top DBR involving tailored stress

We present an optically pumped and continuously tunable 1.55-/spl mu/m vertical-cavity surface-emitting laser (VCSEL). The device shows 26-nm spectral tuning range, 400-/spl mu/W maximum output power, and 57-dBm side-mode suppression ratio. The VCSEL is implemented using a two-chip concept. The movable top mirror membrane is precisely designed to obtain a tailored air-gap length (L'=16 /spl mu/m) and a radius of curvature (ROC=4.5mm) in order to efficiently support the fundamental optical mode of the plane-concave resonator. It consists of a distributed Bragg reflector (DBR) with periodic, differently stressed silicon nitride and silicon dioxide multilayers implemented by plasma-enhanced chemical vapor deposition. The lower InP-based part, comprising the InP-InGaAsP bottom DBR and the active region, is grown monolithically using metal-organic vapor phase epitaxy.     

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.     

Proximity communication

This paper reports results from wireless chip-to-chip communication experiments. Sixteen bit words pass from one chip to another in parallel without detectable error at 1.35 billion data items per second for a total data rate of 21.6 Gigabits per second. The experiment transmits pseudo random patterns between chips built in a 350-nm CMOS technology. Chips touch face-to-face to communicate. The same pseudorandom data pattern is loaded onto both chips so that the receiving chip can check the accuracy of every bit communicated. Each communication channel consumes a static power of 3.6 mW, and a dynamic power of 3.9 pJ per bit communicated. The channels lie on 50-/spl mu/m centers. Because the capacitive communication works through covering oxide, ESD protection is unnecessary. Vernier position measuring circuits built into the chips indicate the relative position of transmitting and receiving arrays to assist mechanical alignment. The test chip includes a Vernier measurement circuit that provides inter-chip position measurements with a resolution of 1.4 /spl mu/m.     

A variable range bi-phasic current stimulus driver circuitry for an implantable retinal prosthetic device

This paper reports a driver circuitry to generate bi-phasic (anodic and cathodic) current pulses for stimulating the retinal layer through electrodes which is part of a retinal prosthetic device for implants in blind patients affected by retinitis pigmentosa (RP) and age-related macular degeneration (AMD). Dual voltage architecture is used to halve the number of interface leads from the chip to the stimulation sites compared to a single voltage supply. The driver circuitry is designed to deliver currents with six bit resolution for a wide range of full scale currents up to 600 /spl mu/A. To cater to the varying stimulus requirements among patients and different regions of the retina, variable gain architecture is used to achieve fine resolution even for a narrow range of stimulus. 1:8 demultiplexing feature is embedded within the output stage thus allowing one DAC for eight outputs. A novel charge cancellation circuitry with current limiting capability is implemented to discharge the electrodes for medical safety. Measurement results of a prototype chip fabricated in 1.5-/spl mu/m CMOS technology are presented.     

Sensitivity of double-gate and FinFETDevices to process variations

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.     

On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique

An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. With this technique, the multiplication efficiency and current driving capability are both independent of the number of multiplier stages. A mathematical model and simple equivalent circuit have been developed for the multiplier and the predicted performance agrees well with measured results. A multiplier has already been incorporated into a TTL compatible nonvolatile quad-latch, in which it occupies a chip area of 600 /spl mu/m/spl times/240 /spl mu/m. It is operated with a clock frequency of 1 MHz and can supply a maximum load current of about 10 /spl mu/A. The output impedance is 3.2 M/spl Omega/.     

General-purpose 128/spl times/128 SIMD processor array with integrated image sensor

A CMOS image sensor/processor chip fabricated in a 0.35 /spl mu/m CMOS technology is presented. The chip contains a general purpose software-programmable SIMD array of 128/spl times/128 processing elements. It executes over 20 GOPS while dissipating 240 mW of power and achieves pixel-processor density of 410 cells/mm/sup 2/. Performance and accuracy measurement results are given.     

An 18K bipolar dynamic random access memory

A 2K/spl times/9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75 ns and 300 ns access and cycle time, respectively. The design is based on a two device cell of 800 /spl mu/m/SUP 2/ size. All chip input and output signals are TTL compatible.     

Three-dimensional wafer stacking via Cu-Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology

The authors report the first demonstration of integrating wafer stacking via Cu bonding with strained-Si/low-k 65-nm CMOS technology. Sets of 330 mm wafers with active devices such as 65-nm MOSFETs and 4-MB SRAMs were bonded face-to-face using copper pads with size ranging between 5 /spl mu/m/spl times/5 /spl mu/m and 6 /spl mu/m/spl times/40 /spl mu/m. The top wafers were thinned to different thicknesses in the range 5 to 28 /spl mu/m. Through-silicon-vias (TSVs) and backside metallization were used to enable electrical testing of both wafers in the Cu-stacked configuration. We tested individual transistors in the thinned silicon of bonded wafer pairs where the thinned silicon thickness ranged from 14 to 19 /spl mu/m. All results showed that both n- and p-channel transistors preserved their electrical characteristics after Cu bonding, thinning, and TSV integration. We also demonstrated the functionality of stacked 65-nm 4-MB SRAMs by independently testing the cells in both the thinned wafer and the bottom wafer. For the SRAM, we tested a wider thinned wafer thickness range from 5 to 28 /spl mu/m. On all tested samples, we did not find any impact to the electrical performance of the arrays resulting from the three-dimensional (3-D) integration process. The stacked SRAM is an experimental demonstration of the use of 3-D integration to effectively double transistor packing density for the same planar footprint. The results presented in this letter enable further exploratory work in high-performance 3-D logic, which takes advantage of the improved interconnect delays offered by this Cu-bonding stacking scheme integrated with modern CMOS processes.     

A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.     

An nMOS VLSI process for fabrication of a 32-bit CPU chip

An overview is given of a silicon-gate NMOS fabrication process used to realize a 450000 transistor, 32-bit single-chip CPU that operates at a worst case 18 MHz clock frequency. The technology utilizes 1.5-/spl mu/m lines and 1.0-/spl mu/m spaces on all critical levels, and provides tungsten dual layer metallization. The device and interconnect structure for this 8-mask process is outlined as a sequence through the process flow. Linewidth and alignment statistics are given for the optical reduction-projection step-and-repeat lithography used in this technology.     

Micropositioning device using impact force of piezoelectric flying wires

In this paper, a micropositioning device for precision positioning of miniaturized parts is proposed. This device uses piezoelectric flying wires to generate impact forces for actuating a target object to be positioned. The proposed device features two main characteristics: the impact force can actuate a half-tightened object with a high degree of precision, and the thin flying wire is suitable for the actuation of miniaturized object. Fundamental properties of the proposed device were examined experimentally and theoretically based on a basic positioning unit. Furthermore, for the practical application in assembly works, the control system for a three degrees-of-freedom micropositioning device with positioning range of (/spl plusmn/250 /spl mu/m, /spl plusmn/250 /spl mu/m, /spl plusmn/30 mrad) along the X-, Y-, and /spl Theta//sub z/-axes was implemented. The target object (16/spl times/24/spl times/6 mm) was successfully positioned with positioning accuracies of (/spl plusmn/1 /spl mu/m, /spl plusmn/1 /spl mu/m, /spl plusmn/0.2 mrad), based on a derived heuristic control model.     

A comparison of front- and backside-illuminated high-saturation power partially depleted absorber photodetectors

A systematic study of high-saturation-current p-i-n In/sub 0.53/Ga/sub 0.47/As photodiodes with a partially depleted absorber (PDA) has been made under front (p-side) and back (n-side) illumination. The photodiode structure consists of an In/sub 0.53/Ga/sub 0.47/As absorption region (450-nm p-InGaAs, 250-nm unintentionally doped InGaAs, and 60-nm n-InGaAs) sandwiched between p- and n-InP layers. For front illumination of a 34-/spl mu/m-diameter photodiode at 2-V bias the saturation currents were 23 and 24 mA at 10 and 1 GHz, respectively. Under similar conditions, backside-illumination resulted in saturation currents of 76 mA (10 GHz) and >160 mA (1 GHz). Backside illumination of a 100-/spl mu/m-diameter photodiode achieved a saturation current >400 mA. For the case of front illumination the device lateral resistance dominates whereas for backside illumination the response is determined primarily by the space charge effect.     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

Experimental analysis of a broadly tunable InGaAsP laser with compositionally varied quantum wells

Custom-designed InGaAsP lasers have been fabricated, tested, and show a broad spectral output at a bias current of 240 mA. The Fabry-Perot ridge waveguide lasers were grown with one 80-/spl Aring/ and five 100-/spl Aring/ quantum wells in the active region. A different material composition was used for each well and this provided contributions to the gain profile over a broad wavelength range. A 1400-/spl mu/m cavity length laser was found to operate in the spectral region from 1475 to 1650 nm and single-mode operation on the individual Fabry-Perot modes of the uncoated laser was achieved over a 172-nm tuning range using a diffractive optical element short external cavity. The side-mode suppression ratio was measured to be above 30 dB at all wavelengths within the tuning range. Complete spectral coverage, in overlapping short segments, with the device is possible using temperature tuning.     

Process and device performance of 1 /spl mu/m channel n-well CMOS technology

The process and device performance of 1 /spl mu/m-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 /spl Omega/-cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from 5/spl times/10/SUP 15/ to 4/spl times/10/SUP 16/ cm/SUP -3/, n-well depths of 3, 4, and 5 /spl mu/m, channel boron implantation doses from 2/spl times/10/SUP 11/ to 1.3/spl times/10/SUP 12/ cm/SUP -2/, and effective channel lengths down to 0.6 /spl mu/m. Based on the experimental results obtained from /spl mu/m-channel n-well CMOS devices, the scaling effects on device and circuit performance of 0.5 /spl mu/m-channel n-well CMOS are discussed and the deep-trench-isolated CMOS structure is demonstrated.     

Tunnel injection active region in an oxide-confined vertical-cavity surface-emitting laser

Data are presented on oxide-confined AlGaAs-GaAs-InGaAs VCSEL's that use high-index half-wave GaAs spacer layers and electronic tunnel injection and confinement. To our knowledge, this is the first demonstration of tunnel injection in a vertical-cavity laser. Threshold currents range from 344 /spl mu/A for a 6.5-/spl mu/m diameter device to 151 /spl mu/A for a 1-/spl mu/m diameter device. The relatively high threshold currents are attributed to a detuned cavity and higher order transverse-mode operation.     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

High-frequency performance of subthreshold SOI MESFETs

Results from silicon-on-insulator (SOI) MESFETs designed for subthreshold operation are presented. The transistors have subthreshold slopes as low as 78 mV/dec and off-state drain currents approaching 1 pA//spl mu/m. Drain current saturation can be achieved with drain voltages of less than 0.5 V and with output impedance>100 M/spl Omega//spl middot//spl mu/m. The cutoff frequency of a 500-nm gate length device exceeds 1 GHz at currents significantly less than 1 /spl mu/A//spl mu/m. These results suggest that subthreshold SOI MESFETs might have useful applications in mixed-signal, micropower circuit design.