基于容差分析的电路参数中心值设计研究

论述了电路参数设计的基本原理,提出了在PSpice 9软件上以容差分析为基础的电路参数中心值的设计方案.详细阐述了蒙特卡罗分析法、合格率的估算法及统计重心搜索法,对以蒙特卡罗分析为基础的电路合格率的统计及元件参数中心值的设计进行了研究.考虑到实际元件的容差分布对电路性能的影响,以OTL电路为例分析实现了电路性能指标满足约束条件下以合格率最大为目标的元件参数值的设计,证明了该方案的可行性.同时获得电路性能指标的统计特性及生产合格率的预测数据,对指导实际生产具有理论价值.     

MCMC粒子滤波算法研究及应用

粒子滤波算法是一种基于贝叶斯估计的蒙特卡罗方法,适用于非线性非高斯系统的分析,被广泛应用于跟踪、定位等问题的研究中。为了解决粒子滤波算法在重采样后,丧失粒子多样性的问题,本文在粒子滤波算法的重采样步骤后,加入了马尔可夫链蒙特卡罗（Markov Chain Monte Carlo,简称MCMC）移动步骤,增加粒子的多样性。利用粒子滤波算法和MCMC粒子滤波算法对目标跟踪问题进行了仿真,并且通过分析仿真实验结果,比较了两种算法的性能,结果说明加入MCMC粒子滤波算法的性能优于粒子滤波算法。     

一个新的电路容差设计的数学模型及其算法

本文提出新的电路参数容差设计的数学模型。从正交表的正交性出发,提出了“正交表用作抽样区域合格率为1的判据”的假设,依此假设为基础结合新的数学模型,建立了新的正交表电路参数容差设计计算法。该算法的特点是:不存在导数计算;避免了在优化过程中为估计合格率而进行的大量电路模拟;能够处理多参数的可变容差设计问题。     

基于QMCPF-IMM的强机动目标跟踪算法研究

为了提高雷达对机动目标的跟踪精度,通过融合拟蒙特卡罗思想,提出了一种适用于非线性非高斯系统的拟蒙特卡罗粒子滤波交互式多模型算法。该算法利用拟蒙特卡罗采样,克服传统算法采样粒子间隙过大、粒子层叠问题,增加交互式多模型对机动目标跟踪时的有效粒子数;通过区间估计理论,解决拟蒙特卡罗支撑区间难以计算问题,并结合核密度估计重采样,保证采样粒子的低等差异性。仿真结果表明：与交互式多模粒子滤波算法相比,改进算法可在保证滤波实时性的同时,提高跟踪精度。     

电路中心设计的一个新算法——中心随机游动

本文提出了一个电路中心设计(DC)的新算法。在正态分布、同一方差的假设下,借助随机逼近理论讨论了它的收敛性。因其只要求对电路进行Monte Carlo分析(MCA),不用计算灵敏度,故适用于线性和非线性电路,易于在计算机上实现。算例表明,本算法收敛快,计算量少,对非凸、非单连通可行域均有效。     

利用综合梯度近似的有效优化

本文提出一种利用综合梯度近似达到高效率优化的灵活而有效的再法．这种算法结合了扰动法、Broyden校正法和Powell的特珠迭代法．扰动法用于徙横一个初始近似以及正则校正．近似梯度是利用Broyden公式连同PowcK特殊连代法一起校正的．对Broyden校正法引进修正值．是为了更好地利用雅可比的可能稀硫同题．应甩这种算法，便可得到有效的以梯度为基础的计算机辅助设计(CAD）电路用非线性优化工具，而不需要费力去计算精确导数．文中以实例说明了应用的实际意义．实捌包括采用技术和多数电路同时处理的FET小信号模型建立、微波放大嚣的最坏态设计和五信遗多路调制器的极小极大优化．与完全用扰动法估计导数相比．极大地改善了计算效率。     

中心设计方法的研究

本文提出了一种提高电路成品率的中心设计方法。首先建立了优选初始点的目标函数,对此函数优化。并以此结果作为中心设计的初始点。其次,把蒙特卡罗法与泰勒级数近似式结合起来,估计生产成品率,选择元件标称值。最后编制程序MAIN,计算表明该方法正确、有效。     

基于粒子滤波算法的DS-CDMA多用户检测

粒子滤波算法是一种基于贝叶斯估计的蒙特卡罗方法,尤其适用于处理非线性、非高斯系统的状态估计问题。该算法应用于DS-CDMA系统的多用户检测中,检测器能在检测性能和计算复杂度之间取得很好的平衡。基于粒子滤波算法的多用户检测器在性能上逼近于最优多用户检测器,而计算复杂度远低于最优多用户检测器,与次优多用户检测器相当。利用白化匹配滤波器的输出可以建立同步DS-CDMA系统的状态空间方程,使得粒子滤波算法应用于多用户检测中。仿真实例证明了基于粒子滤波算法的多用户检测器在等功率和远近效应的情况下的性能优势。     

基于PSpice的电路特性分析和器件性能研究

为了实现计算机对电路的特性进行分析,利用PSpice对RLC电路的交流分析、频率响应以及谐振频率进行模拟,模拟结果和理论值相吻合,PSpice仿真能得到与实际器件操作相同的效果。为了对电路元件的性能进行评估,利用PSpice进行了蒙特卡罗高级分析,分析结果表明：RLC电路器件的合格率和批量元件频率的偏差相关联,并与其容差相联系,PSpice是研究器件性能的有效工具。     

用时域-谱平衡法分析 FDMA 数字调制信号激励的微波非线性电路

本文提出一种用于微波非线笥电路分析的时域－谱平衡算法,这种算法可以用于各种数字调制信号激励的微波非线性电路的分析,尤其适用于频分多址的数字调制信号的分析。利用算法,分析了ＱＰＳＫ信号激励的微波放大器,所得模拟结果与理论分析吻合。     

MCA-newton method for circuit yield estimation and optimization

 An algorithm for circuits yield estimation and optimization is described.To obtain the first and second derivatives of yield with respect to center and obtain maximum production yield,Monte Carlo analysis (MCA)and Newton method are employed.By using“fail”samples and rearrange frequences in order of nonincreasing weights,the estimator is improved and the number of circuit analysis is reduced.Both theoretical analysis and calculation examples show that the estimator is correct and the proposed algorithm performs well and can be used for middle-scale circuit design.No matter the region of acceptability is convex ononconvex,the circuit is linear or nonlinear,the algorithm is available.     

Maximum likelihood estimation for failure analysis [IC yield]

This paper presents an iterative maximum likelihood (ML) estimation method for statistical analysis of yield loss. By means of inductive fault analysis (IFA) and circuit simulation, the mapping between defect types to the corresponding fault signature is constructed. Using the count of each fault signature occurrence, which is provided by a tester on defective ICs, the most likely causes of low yield are identified automatically without the need for physically deprocessing the defective IC's. We present an experiment on an SRAM cell array to illustrate the effectiveness of the iterative ML algorithm     

Rapid yield estimation as a computer aid for analog circuit design

A rapid yield estimation methodology that aids the analog circuit designer in making design tradeoffs that improve yield is presented. This methodology is based on using hierarchical evaluation of analysis equations, rather than simulations, to predict circuit performance. The new analog rapid yield estimation (ARYE) method has been used to predict the yield of two-stage operational amplifiers and has been incorporated into the Carnegie Mellon University (CMU) analog design system (ACACIA). An example of how ARYE allows analog designers to quickly explore the impact of design changes on yield is presented. The primary goal of ARYE is to make numerous early predictions of parametric yield economical for the analog circuit designer     

Hierarchical yield estimation of large analog integrated circuits

A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive     

IC优化设计及其成品率预测

IC成品率是与电路性能和制造成本及制造效益紧密相关的一个重要因素,在进行IC优化设计时,可将成品率与制造效益作为协调各性能指标的优化目标.针对这一问题,本文完善了IC成品率效益协调优化设计模型,提出了一种实现该模型的IC优化设计和成品率预测方法,并利用OrCAD/PSpice中的统计分析和电路性能分析的功能和特点,建立了相应的算法.实例表明,该方法及其实现算法是有效的.     

Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis

This paper focuses on the implementation of different techniques for the integration of yield estimation in the synthesis loop of analog integrated circuits (ICs). MOEA/D (Multi-Objective Evolutionary Algorithm with Decomposition) is considered to be a very powerful multi-objective optimization algorithm. For the consideration of yield, several techniques are discussed and three different yield-aware Pareto front (PF) generation techniques have been implemented on the MOEA/D optimizer. The implemented yield-aware PF techniques are compared by designing a fully-differential folded-cascode amplifier with different number of objectives. In order to embed the variation effects into the optimization loop, the statistical analysis of the circuit has been carried out by using a Quasi Monte Carlo (QMC) technique. The results suggest that especially two of these techniques look promising for high dimensional robust optimization of analog circuits.     

Efficient SRAM yield optimization with mixture surrogate modeling

Largely repeated cells such as SRAM cells usually require extremely low failure-rate to ensure a moderate chi yield. Though fast Monte Carlo methods such as importance sampling and its variants can be used for yield estimation, they are still very expensive if one needs to perform optimization based on such estimations. Typically the process of yield calculation requires a lot of SPICE simulation. The circuit SPICE simulation analysis accounted for the largest proportion of time in the process yield calculation. In the paper, a new method is proposed to address this issue. The key idea is to establish an efficient mixture surrogate model. The surrogate model is based on the design variables and process variables. This model construction method is based on the SPICE simulation to get a certain amount of sample points, these points are trained for mixture surrogate model by the lasso algorithm. Experimental results show that the proposed model is able to calculate accurate yield successfully and it brings significant speed ups to the calculation of failure rate. Based on the model, we made a further accelerated algorithm to further enhance the speed of the yield calculation. It is suitable for high-dimensional process variables and multi-performance applications.     

一种有效的电路容错结构及其成品率分析

本文提出了一种有效的电路容错结构,给出了一种重组算法.按照这种重组算法,对该结构的成品率进行了分析,并给出了其成品率的表达式.最后,通过电路设计和分析说明了该容错结构的有效性.     

An iterative approach to VLSI circuit lifetime estimation

In this paper, the problem of VLSI circuit lifetime estimation is discussed. It is shown that lifetime determination is equivalent to finding the smallest zero of a continuous non-differentiable function for a specific circuit realization. An iterative multiple cubic spline approximation algorithm is proposed to determine the lifetime. Application in VLSI circuit analysis is given, in which the degradation resulting from the hot electron effects are considered. The results show that our proposed approach is efficient.     

Nonlinear statistical modeling and yield estimation technique foruse in Monte Carlo simulations [microwave devices and ICs]

A novel nonlinear statistical modeling technique for microwave devices and a new approach to yield estimation for microwave integrated circuits are presented. The statistical modeling methodology is based on a combination of applied multivariate methods with heuristic techniques. These include principal component analysis and factor analysis in conjunction with maximally flat quadratic interpolation and group method of data handling. The proposed modeling approach, when applied to the database of extracted equivalent circuit parameters (ECPs) for a pseudomorphic high electron mobility transistor device, has proven that it can generate simulated ECPs, S-parameters, that are statistically indistinguishable from measured ones. A new yield estimation technique based on a Latin hypercube sampling (LHS) is also demonstrated. The LHS-based simulation is utilized as an alternative to primitive Monte Carlo (PMC) simulation in yield analysis. An equally confident yield estimate based on the LHS method requires only one-fourth of those simulations needed when the PMC technique is used