High-efficiency millimeter-wave GaAs/GaAlAs power HEMT's

The power, gain, and efficiency of 0.5-µm gate-length, 75- and 50-µm gate-width multiple heterojunction high electron mobility transistors (HEMT's) have been evaluated from 10 to 60 GHz. At 10 GHz, with a source-to-drain voltage as low as 2.4 V, the device delivers a power density of 0.37 W/mm with 13.4-dB gain and 60.8-percent efficiency. At 60 GHz, a 50-µm device gave 0.4 W/mm with 3.6-dB gain and 14-percent efficiency. The power density and efficiency of these 0.5- µm gate-length HEMT's above 40 GHz are the best reported for a three-terminal device. Fundamental frequency oscillations up to 104 GHz were observed when a device was bonded as a free-running oscillator.     

A low-noise GaAs MESFET made with graded-channel doping profiles

We have demonstrated that devices fabricated from epitaxially grown material with a graded-channel doping profile are capable of improved microwave performance. For operation at 12 GHz, graded-channel doping profile devices have an associated gain that is always 1 dB higher at the minimum noise-figure point compared to ion-implanted Gaussian-channel doping profile devices. A noise figure of 1.60 dB with 11-dB associated gain has been obtained at 12 GHz for 0.5-µm × 300-µm gate devices. A tranconductance of 200 mS/mm for this device has been achieved.     

Device fabrication in {100} silicon-on-oxide produced by a scanning CW-laser-induced lateral seeding technique

By using a CW-laser-beam-induced lateral seeding technique, which is a zone-melting crystal-growth process, single-crystal silicon-on-oxide with{100}orientation has been obtained. To adopt this process for silicon-on-insulator (SOI) MOS transistor fabrication, a masking level has been added to an exisiting n-MOSFET mask set so that a fully recessed oxide layer may be grown in selected regions of a silicon wafer; the exposed silicon region becomes the seed region. After depositing a 0.5-µm-thick layer of undoped low-pressure CVD polysilicon on the wafer, a laser process is performed to induce epitaxial growth in the polysilicon-on-silicon region, which in turn seeds the zone growth of the polysilicon-on-oxide region as the beam is traversed across the surface of the wafer. N-channel MOS transistors have been fabricated in the silicon-on-oxide material using projection printing lithography. Both complete-island-etch (CIE) and LOCOS techniques have been used for device-to-device and device-to-substrate isolation. Surface electron mobilities as high as 740 cm²/V . s, comparable to that obtainable in bulk-type devices, have been measured in 5-µm channel-length devices. It is shown that the back interface between the recrystallized silicon and the oxide layer is the dominant contributor to the subthreshold leakage current due to a combined effect of a high fixed oxide charge density and drain-induced barrier lowering. A high dose (sim 10^{12}cm^-2) deep boron implantation centered at the back interface and a back-gate bias have been shown to be effective in suppressing the leakage current to as low as 1-pA/µm channel width at VDS= 2 V, comparable to the best results obtained in silicon-on-sapphire (SOS).     

Performance of the focused-ion-striped transistor (FIST)—A new MESFET structure produced by focused-ion-beam implantation

We report the fabrication and performance of the focused-ion-striped transistor (FIST), which is a GaAs MESFET structure having a channel with stripes of high conductance, going from the source to the drain, separated by regions of semi-insulating material. Calculations show that this structure produces a depletion layer that wraps around the conducting channel stripes and this should result in improved transconductance and output resistance. Experimental results are reported for devices having 1-µm gates and the FIST channels produced by focused-ion-beam implants of silicon with a width of 0.2 µm and a spacing that is varied from 0.2 to 0.5 µm. These verify the basic performance characteristics of the FIST including an increase in stripe transconductance, a two-fold increase in output resistance, and larger values of fTfor small values of Idsnear pinchoff.     

CMOS on buried nitride—A VLSI SOI technology

A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.     

High-speed polysilicon emitter—base bipolar transistor

High-speed polysilicon emitter and base electrode Si n-p-n bipolar devices were fabricated showing performances of 55-ps ECL gate delay (FI = FO = 1) and cutoff frequency of 15.6 GHz (at VCE= 3 V, LVCEO= 6.8 V). These devices were built on an oxide-isolated substrate produced by planarizing oxide which is deposited after device Si island etching. The final emitter width is 0.5 µm, and a 1.3-µm-thick arsenic-doped LPCVD epitaxial layer of 0.25 Ω.cm is utilized. Emitter-base (E-B) junctions formed by direct implantations of arsenic and boron ions into a substrate were compared with junctions induced by diffusing dopants from implanted polysilicon. In the case of diffused junctions, an emitter junction depth of less than 500 Å along with a 1000-Å base width can be obtained.     

A comparison of Nd:YAG fundamental and second-harmonic Q-switched laser-beam lifetime doping in single-crystal silicon

Silicon devices including bipolar transistors, junction diodes, and MOS capacitors were scanned by aQ-switched Nd:YAG (1.06 µm) and frequency-doubled Nd:YAG (0.53 µm) radiations under various conditions. The electrical characteristics of these devices were measured before and after scanning and again after thermal annealing. The data includes transistor gain versus laser power; junction diode leakage current versus junction depth; MOSC-Vlifetime versus laser power and the effects of subsequent thermal anneals on all of these. The results are that bulk minority-carrier lifetime decreases of several orders of magnitude will be produced by either of these radiations at peak power levels below those which will produce any visible surface damage. The changes in minority-carrier lifetime are stable for post scanning thermal anneals up to 400°C and are almost completely removed from an 800°C anneal. The depths within which minority-carrier lifetime changes significantly are 0.7 and 1.8 µm for 0.53- and 1.06-µm wavelength laser radiations, respectively. The results indicate that the recombination centers produced by the scanning are point defects and their density decreases exponentially with the distance into the silicon. The average power thresholds for point defect production (for both 0.53- and 1.06-µm wavelengths) were determined and are observed to increase with increased laser wavelength and pulse width. Potential applications in silicon devices and integrated circuits such as selective lifetime doping, β trimming, and selective-link making without passivation damage are possible.     

Noise figure characteristics of 1/2-µm gate single-heterojunction high-electron-mobility FET's at 35 GHz

In this letter, we report room-temperature noise figure performance of Gallium Arsenide single-heterojunction high-electron-mobility transistors (HEMT's). We have measured a noise figure of 2 dB at 35 GHz with 5 dB of associated gain. The devices tested were 150 µm wide with 0.5-µm-long gates. The active layers were grown by molecular beam epitaxy (MBE). These values are the best reported results for either HEMT's or MESFET's at these frequencies, regardless of their geometry.     

Submicrometer polysilicon gate CMOS/SOS technology

A process is described for the fabrication of CMOS/SOS submicrometer devices and integrated circuits. The process utilizes the lateral diffusion of boron into polycrystalline silicon and a subsequent anisotropic etchant to define the narrow poly gates. Devices with channel lengths as small as 0.3 µm have been fabricated and characterized. Both avalanche and tunnel injection of carriers into the gate dielectric have been measured and both can have an impact on the limit of voltage operation. At present, these mechanisms appear to place an upper limit of about 8 V on the operating voltage of dynamic circuits containing 0.5- µm channel length devices. The propagation delay of 0.5-µm channel length CMOS/SOS inverters is about 200 ps at 5 V and dynamic binary counters will operate with a maximum input frequency of 550 MHz and 8 V while dissipating 130 mW.     

Channel-length effects in quarter-micrometer gate-length GaAs MESFET's

The electrical performance of 0.25-µm gate-length GaAs MESFET's with channel lengths (i.e., source-drain spacings) of 2.1 and 0.5µm is compared. An extremely short channel length has been found experimentally to lead to significant increases in the electron average drift velocity, transconductance, and forward transducer gain. Increases in both the electron average drift velocity and intrinsic dc transconductance of ∼70 percent were observed in these 0.25-µm gate-length devices when the source-drain spacing was reduced from 2.1 to 0.5µm. Deleterious effects such as increased output conductance and interelectrode capacitances were also noted.     

Ga0.4In0.6As/Al0.55In0.45As pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic Ga0.4In0.6As/ Al0.55In0.45As modulation-doped field-effect transistors (MODFET's) grown by MBE on InP have been fabricated and characterized. DC transconductances as high as 271, 227, and 197 mS/mm were obtained at 300K for 1.6-µm and 2.9-µm gate-length enhancement-mode and 2-µm depletion-mode devices, respectively. An average electron velocity as high as 2.36 × 10⁷cm/s has been inferred for the 1.6-µm devices, which is higher than previously reported values for 1-µm gate-length Ga0.47In0.53As/Al0.48In0.52As MODFET's. The higher bandgap Al0.55In0.45As pseudomorphic barrier also offers the advantages of a larger conduction-band discontinuity and a higher Schottky barrier height.     

35-GHz performance of single and quadruple power heterojunction HEMT's

The potential of single hetrojunction (SHJ) and quadruple heterojunction (QHJ) HEMT devices to provide power amplification at theKa-band frequencies has been measured. The power level observed, from QHJ devices that have gate lengths of 0.5 µm and gate widths of 200 µm, has been over +20 dBm when gain is compressed below the small signal level by 2 dB. The small-signal gain was 5.2 dB at 35 GHz. The power level demonstrated by the SHJ devices is lower than that of the QHJ devices due to the lower "two-dimensional electron gas" sheet carrier density. Our measurements have shown a saturated power level of +15.3 dBm devices of the same geometry as the above-mentioned QHJ devices. The power performance in both cases (QHJ and SHJ) has been obtained with high efficiencies of 38 and 21 percent, respectively. These performance data represent the highest levels of gain and power reported atKa-band frequencies from transistors that employ a 0.5-µm geometry.     

GaAs MESFET's made by ion implantation into MOCVD Buffer layers

Low-noise GaAs metal-semiconductor field-effect transistors (MESFET's) have been made using ion-implanted metal organic chemical vapor deposition (MOCVD) buffer layers. A noise figure of 1.46 dB with 10.20 associated gain has been achieved at 12 GHz for a 0.5-µm gatelength by 300-µm gatewidth FET device. This result demonstrates that excellent GaAs LNFET's can be made by ion implantation into MOCVD buffer layers, comparable to the best results obtained from similar devices made by AsCl3vapor-phase epitaxy and molecular-beam epitaxy.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

Planar fully ion implanted InP power junction FET's

This letter reports on the fabrication and performance of planar all ion-implanted 1.0-µm gate length InP power junction field effect transistors (JFET's). The devices were fabricated utilizing n+ implantation, a AuZn/TiW/Au gate metallization, and an n+ drain ledge. At 4.5 GHz, the 300-µm gate width JFET's exhibited maximum insertion gains of up to 13 dB and scaled output powers as high as 1 W/mm with 3-dB gain.     

Ballistic transport and properties of submicrometer Silicon MOSFET's from 300 to 4.2 K

The characteristics of submicrometer silicon MOSFET's have been measured from 300 to 4.2 K, and the mobility versus temperature and carrier velocity versus longitudinal field as a function of temperature have been plotted. Effective mobilities in 500-µm-square devices as high as 25 000 cm²/V . s at 4.2 K have been observed. Mobilities of this magnitude represent mean free path lengths that could lead to ballistic transport in submicrometer devices. Effective mobilities in 0.2-µm devices were only 800 cm²/V . s at 4.2 K due to high-field effects. The mobility versus effective channel length for 0.2-, 0.7-, and 1.7-µm devices operating at drain voltages of 0.1 V has been plotted, and it has been observed that the mobility is greatly reduced in short-channel devices. The mobility versus longitudinal field was studied, resulting in the observation that ballistic transport is inhibited by the high fields in devices operating at 0.1 V. Similar high-field effects should limit the effects of ballistic transport in high-mobility semiconductors such as submicrometer GaAs FET's Operating at nominal supply voltages.     

4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

Highly reliable high-voltage transistors by use of the SIPOS process

The n-p-n and p-n-p high-voltage transistors showing high reliabilities have been developed by using semi-insulating polycrystalline-silicon (SIPOS) films for the surface passivation. SIPOS films are chemically vapor-deposited polycrystalline-silicon doped with oxygen or nitrogen atoms. The films employed for the surface passivation of high-voltage transistors are composed of triple layers, which are oxygen-doped SIPOS films of 0.5-µm thickness to stabilize the silicon interface, nitrogen-doped SIPOS films of 0.15-µm thickness to prevent water or sodium ions from reaching the silicon surface, and silicon dioxide films to prevent dielectric breakdown of the SIPOS films under very high-voltage operation. The n-p-n and p-n-p SIPOS transistors rated at 800 and 2500 V have been produced in planar-like structures with field-limiting rings. These transistors showed highly reliable characteristics, because the passivating SIPOS layer provides a good protection against ionic contamination and externally applied electric fields. Furthermore, 10-kV n-p-n SIPOS transistors with multiple rings have been fabricated and found that operation is stable.     

A three mask bipolar integrated circuit structure

A new bipolar integrated circuit structure has been fabricated that compares favorably to the MOS structure in terms of fabrication simplicity and performance. The new structure is basically a modified isolated lateral transistor and requires only three photolithographic masking operations up to and including first level of metalization. The fabrication of the structure is as follows: a shallow nonselective p-type base region is diffused into a lightly doped p-type substrate; n⁺emitter and collector regions are then simultaneously and selectively diffused into and through the p-type base region thus forming a lateral n-p-n transistor. The second and third masks define the contact holes and the metalization pattern, respectively. Lateral isolation of the structure is obtained by encircling the emitter and base regions with the collector region. Vertical isolation is achieved by the large collector-depletion region that extends beneath the emitter and base regions. Since the substrate is lightly doped a low collector voltage will adequately isolate the emitter and base regions from adjacent devices. The new technology permits the fabrication of transistors, resistors, and crossunders. Transistors with 2-to 3-µm spacings occupy 500 µm²of silicon area and have the following characteristics:beta = 35, peakf_{t} = 0.1GHz at 0.5 mA, BV(SUSTAIN) = 3 to 5 V,t_{r} = 20ns,t_{f} = 120ns,t_{s} = 20ns. Resistors with values as high as 40 kΩ have been fabricated within 600 µm². Active nonlinear loads with effective resistance up to 200 kΩ have been fabricated. TTL gates have been made with power-delay products of 3.6 pJ, and propagation delays of 34 ns.     

Lateral PNP GaAs bipolar transistor with minimized substrate current

Lateral pnp bipolar transistors have been fabricated using Be implantation to define the emitter and collector areas. The base area (1 - 2 µm wide) has been protected against Be ions during implantation by SiO2and photoresist. The lateral straggling and diffusion during the anneling process reduces the base width, which can be adjusted with the annealing temperature and time. Between the active n-GaAs layer and substrate, a n-Ga0.7Al0.3As layer is deposited. The Be ions penetrating the GaAs/GaAlAs interface form a pn junction in the GaAlAs layer below the emitter and collector area. This reduces the current by several orders of magnitude through the parasitic emitter-substrate (base) diode compared to a GaAs pn junction, due to the higher band gap. For these devices with an effective base width of 0.5 µm, a current gain of 10 in common emitter configuration has been obtained.