A lifetime prediction method for oxide electron trap damage createdduring hot-electron stressing of n-MOS transistors

Electron trap creation under conditions of hot-electron stress (i.e., stress at V_d=V_g) is examined. It is shown that a relationship exists linking lifetime to the injected gate current and drain current, offering a lifetime prediction method for these types of traps. Comparing this type of damage to interface trap (N_it) creation, it is found that larger energies (approximately 1.5 times that for N_it) are required to generate this defect. It is shown that an extrapolation technique can be used to obtain gate currents at working circuit voltages, extending the prediction of lifetimes for oxide trap creation to low voltages     

Characterization of interface trap dynamics responsible for hysteresis in organic thin-film transistors

In this paper, the current hysteresis of organic thin film transistors (OTFTs) formed by TIPS-Pentacene has been demonstrated by bi-directional gate-voltage scan and explained using the trapping and detrapping mechanism. The trapping and detrapping rates have been further verified by the gate-voltage sampling method and the channel charge pumping method. The validity of the methods to characterize interface states of OTFTs that lead to the hysteresis is justified. The two independent methods consistently reveal that the hole trapping and release rates at the interface between the channel of the OTFTs to the gate dielectric are asymmetric.     

On the hot-carrier-induced post-stress interface trap generation inn-channel MOS transistors

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D_it-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior     

Identification and localisation of gate oxide weaknesses in n-MOS transistors through Fowler-Nordheim tunnelling and SPICE simulation

Analysis of the I/V characteristics after Fowler-Nordheim (F-N) injection of n-MOS transistors with weak source-drain overlap regions show the presence of an anomalous 'hump' SPICE simulations show that the same hump can arise in localised damage regions along the source-drain periphery, and that this is possibly in the bird's beak region. The results suggest that SPICE simulations and F-N injection can be used to study localised damage in MOS transistors.<>     

On the mechanism for interface trap generation in MOS transistorsdue to channel hot carrier stressing

The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from “hot carrier injection.” We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing     

Transient isothermal generation at the silicon-silicon oxide interface and the direct determination of interface trap distribution

The theory of transient isothermal generation through the interface traps at the semiconductor-insulator interface is presented. The generation current (I_g) vs time (t) characteristic is obtained in terms of the interface trap distribution throughout the bandgap. It is shown that a plot of I_et vs log_et is a direct image of the energy distribution of the traps in the upper-half of the bandgap (in the case of an n-type semiconductor) and a plot of I_gt vs log_et is a direct image of the trap distribution in the lower-half of the bandgap.     

Examination of the time power law dependencies in hot carrierstressing of n-MOS transistors

The origins of the different power laws arising from hot carrier stressing at low and high gate voltages are examined. It is found that damage at V_g=V_d (predominantly electron trapping in the oxide) has the same underlying 0.5 power law exponent dependence as stress under I_b(max) (interface state creation) conditions, if degradation is measured as a function of injected electronic charge instead of time. It is proposed that the reduced gradient normally seen under V_g=V_d stresses arises due to the repulsive electrostatic oxide fields created by the trapped oxide charge and does not reflect the fundamental rate of trap creation. Stressing at low gate voltages (V_g=V_d/5) also reveals the presence of a similar time power law of exponent 0.5 when the oxide trap contribution alone is separated out from the rest of the damage. It is concluded that the 0.5 power law appears to be the fundamental underlying kinetic equation that is seen throughout the gate voltage stress range, despite the different types of damage and the very different trap creation mechanisms     

Effects of forward biasing the substrate on the low temperaturebehaviour of n-MOS transistors

The effect on the electrical behaviour of forward-biasing the substrate of the n-MOSFET at varying temperatures is investigated. Results of the DC characteristics are presented for several forward and reverse substrate voltages over a wide temperature range from room temperature to 5 K     

Reconciliation of different gate-voltage dependencies of 1/f noisein n-MOS and p-MOS transistors

We have examined the 1/f noise of 3 μm×16 μm, n- and p-MOS transistors as a function of frequency (f), gate-voltage (V_g ) and temperature (T). Measurements were performed for 3 Hz⩽f⩽50 kHz, 100 mV⩽|V_g-V_th|⩽4 V, and 77 K⩽T⩽300 K, where V_th is the threshold voltage. Devices were operated in strong inversion in their linear regimes. At room temperature we find that, for n-MOS transistors, S(V_d)∝V_d²/(V_g-V_th )², and for p-MOS transistors, we generally find that S(V_d)∝V_d²/(V_g-V_th , consistent with trends reported by others. At lower temperatures, however, the results can be very different. In fact, we find that the temperature dependence of the noise and the gate-voltage dependence of the noise show similar features, consistent with the idea that the noise at a given T and V_g is determined by the trap density, D_t(E), at trap energies E=E(T,V_g). Both the T- and V_g-dependencies of the noise imply that D_t (E) tends to be constant near the silicon conduction band edge, but increases as E approaches the valence band edge. It is evidently these differences in D_t(E) that lead to differences in the gate-voltage dependence of the noise commonly observed at room temperature for n- and p-MOS transistors     

Effect of high field stresses on interface states of n-MOS capacitors

High electrical stresses have been applied to n-MOS capacitors prepared following two thermal oxidation methods. The increase of the interface state density was investigated by means of a conductance method and incidentally by a quasi-static method. A threshold effect, possibly related to a Fowler-Nordheim injection, has been found in the increase of this density versus field stress. At high field stresses, a second conductance peak has been observed, which can be explained in terms of new interface states, rather than lateral nonuniformities.     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

Series equivalent circuit representation of SiO2Si interface and oxide trap states

The small-signal frequency response of silicon dioxide-silicon interface and oxide trap states has been investigated and interpreted using a series R-C equivalent circuit model instead of the commonly used parallel R-C equivalent circuit model. It is shown that the series equivalent circuit model is advantageous in extracting the time constants of the oxide traps located in the silicon dioxide layer from experimental data and allows a determination of the spatial extension of the oxide traps. Comparisons of a two-step model, consisting of the Shockley-Read-Hall transition between the band and the interface states and the elastic tunneling transition between the interface and oxide trap states, with experimental data are given to illustrate the range of experimental data required to evaluate an unique set of tunneling and SRH parameters.     

Bipolar stressing, breakdown, and trap generation in thin siliconoxides

Thin silicon oxide films were stressed with bipolar pulses in which the magnitudes of both the positive and negative pulses were independently varied, The time-to-breakdown, the charge-to-breakdown, and the number of traps generated inside of the oxides during the stresses were measured and compared with oxides that had been stressed with unipolar pulses or stressed with constant dc voltages. For the bipolar stresses it was found that the time-to-breakdown, the charge-to-breakdown, and the number of traps generated inside of the oxide all increased as the magnitude of the opposite polarity, nonstressing pulse was increased, until the opposite polarity pulse became large enough to become the stressing pulse. The time-to-breakdown reached a maximum when the magnitude of the stressing pulse was approximately 1 V larger than the magnitude of the nonstressing pulse. The model that was used to explain these increases involved generation of traps inside of the oxide and the lack of spatial correlation between the traps generated by injection from one interface with the traps generated by injection from the other interface     

Characterization of the MIC/MILC interface and its effects on theperformance of MILC thin-film transistors

Process and material characterization of the crystallization of amorphous silicon by metal-induced crystallization (MIC) and metal-induced lateral crystallization (MILC) using evaporated Ni has been performed. An activation energy of about 2 eV has been obtained for the MILC rate. The Ni content in the MILC area is about 0.02 atomic %, significantly higher than the solid solubility limit of Ni in crystalline Si at the crystallization temperature of 500°C. A prominent Ni peak has been detected at the MILC front using scanning secondary ion mass spectrometry. The MIC/MILC interface has been determined to be highly defective, comprising a continuous grain boundary with high Ni concentration. The effects of the relative locations of this interface and the metallurgical junctions on TFT performance have been studied     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

Hot-carrier-induced interface state generation in submicrometerreoxidized nitrided oxide transistors stressed at 77 K

The hot carrier degradation at 77 K of silicon MOSFETs fabricated with reoxidized nitrided oxide (ONO) gate dielectrics has been investigated. Measurements have been performed at both room and LN₂ temperatures on n-channel FETs for both ONO and conventional SiO ₂ films. It is found that the hot-carrier immunity of ONO transistors is substantially larger than that of conventional SiO₂ devices, and that the degree of improvement is much larger at room temperature that an 77 K. While the interface state generation does increase dramatically as a result of 77-K stressing, the dominant degradation mechanism can be attributed to a large increase in the drain resistance of the device due to localized charge trapping at the drain side of the channel     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

A method for separating the effects of interface from border and oxide trapped charge densities in mos transistors

This paper presents a procedure for a more accurate separation of interface trap effects in the presence of large border trap densities after irradiation of MOS devices. It is based on the standard subthreshold technique, but a special measurement procedure is applied which eliminates the drifts produced by border traps via the tunneling effect. The procedure is demonstrated on pMOS dosimetric transistors, and it is shown that it gives different and, we claim, better estimates of interface trap density than standard techniques.     

Characterization of oxide trap energy by analysis of the SILC roll-off regime in flash memories

We present a novel experimental technique to identify the energy of traps responsible for the stress-induced leakage current (SILC) in Flash memories, based on a standard gate-stress analysis with a drain bias used to accelerate channel electrons. From the study of the rolloff in SILC characteristics, we provide evidence for the existence of high-energy traps in the silicon dioxide, located at energies above the silicon conduction band minimum. The new technique is able to characterize the position of defects along the channel and the electron effective temperature at the SILC spot, allowing to extract the dependence of channel electron temperature on the distance from the drain.     

Evolution of oxide charge trapping under bias temperature stressing

Transient oxide-charge trapping and detrapping, commonly regarded as a parasitic effect in the interpretation of dynamic bias-temperature stress (BTS) data, may play an important role on the long term reliability of the gate oxide as revealed by recent studies on the SiON and HfO₂ gate dielectrics. Specifically, it is found that transient charge trapping (one which relaxes upon removal of the applied electrical stress) is transformed into more permanent trapped charge when the applied electrical cum thermal stress exceeds a certain threshold. Below the threshold, cyclical transient charge trapping and detrapping behavior is observed. The observations imply that the oxide structure may be modified by the applied stress, making it susceptible to permanent defect generation. In addition, it is found that when the transformation of hole trapping occurs under negative-bias temperature stress, a correlated increase of the gate current is always observed, which points to the transformation process being the origin for bulk oxide trap generation. However, when the transformation of electron trapping occurs under positive-bias temperature stress, an increase of the gate current is not always observed. From ab initio simulation, we show that an intrinsic oxide defect – the oxygen vacancy-interstitial (V_O − O_i) – could consistently explain the experimental observations. An interesting feature of the V_O − O_i defect is that it can exists in various metastable configurations with the interstitial oxygen O_i in different positions around the vacancy V_O, corresponding to different trap energy states in the oxide bandgap. This characteristic is able to account for the BTS induced generation of deep-level trapped charges as well as transformation of transient (or shallow) to permanent (or deep) charge trapping.