共查询到20条相似文献,搜索用时 15 毫秒
1.
Marchetaux J.-C. Bourcerie M. Boudou A. Vuillaume D. 《Electron Device Letters, IEEE》1990,11(9):406-408
The evolution of the gate current-voltage (I g- V gs) characteristics of n-MOSFETs induced by DC stresses at different gate voltage over drain voltage (V ds ) ratios is studied by the floating-gate (FG) measurement technique. It is shown that the I g-V gs curves are always lowered after aging, and that the kinetics are dependent on the aging conditions. A time power law is representative of the V gs=V ds case. It is demonstrated that electron traps are created in the oxide by both hot-hole and hot-electron injection stresses. They are not present in the devices before aging. They can be easily charged and discharged by short electron and hole injections, respectively 相似文献
2.
Vuillaume D. Marchetaux J.-C. Lippens P.-E. Bravaix A. Boudou A. 《Electron Devices, IEEE Transactions on》1993,40(4):773-781
The creation of defects by hot-carrier effect in submicrometer (0.85-μm) LDD n-MOSFETs is analyzed by the floating-gate and the charge-pumping techniques. It is emphasized that the floating-gate technique is an attractive tool for characterizing the oxide traps located in the drain-gate overlap region, near the oxide spacer of the LDD structures. This work gives new insight into the creation of acceptorlike oxide traps which are electrically active only after electron injection phases. These defects are generated in the whole stress gate bias range (from V d/8 to V d) by hot-hole and/or hot-electron injections, and their generation rates (10-9 and 10-2 for electron and hole injections, respectively) are one decade greater than for the interface state generation. Two-dimensional simulations show that they are mainly responsible for the I d-V g degradation of the LDD MOSFETs, and that the trap concentrations deduced from charge-pumping experiments are consistent with the I d-V g degradation 相似文献
3.
Electron trap creation under conditions of hot-electron stress (i.e., stress at V d=V g) is examined. It is shown that a relationship exists linking lifetime to the injected gate current and drain current, offering a lifetime prediction method for these types of traps. Comparing this type of damage to interface trap (N it) creation, it is found that larger energies (approximately 1.5 times that for N it) are required to generate this defect. It is shown that an extrapolation technique can be used to obtain gate currents at working circuit voltages, extending the prediction of lifetimes for oxide trap creation to low voltages 相似文献
4.
Busta H.H. Pogemiller J.E. Zimmerman B.J. 《Electron Devices, IEEE Transactions on》1993,40(8):1537-1542
The field at the tip of a field emitter triode can be expressed by E =βV g+γV c, where V g and V c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, γV c<<βV g. The-device is operated in the gate-induced field emission mode and the corresponding I -V c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I -V c and transconductance g m-V g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly 相似文献
5.
It is reported that fluorine can jeopardize p+-gate devices under moderate annealing temperatures. MOSFETs with BF2 or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 12 cm-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I -V characteristics of PMOSFET with fluorine incorporated p+-gate revealed that the long gate-length device had abnormal abrupt turn-on I d-V g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I d-V g characteristics associated with long-gate-length p+-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C -V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p+-gate devices is presented. The incorporation of fluorine in the p+ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states 相似文献
6.
Dependence of ionization current on gate bias in GaAs MESFETs 总被引:1,自引:0,他引:1
Canali C. Neviani A. Tedesco C. Zanoni E. Centronio A. Lanzieri C. 《Electron Devices, IEEE Transactions on》1993,40(3):498-501
The nonmonotonic behavior of gate current I g as a function of gate-to-source voltage V gs is reported for depletion-mode double-implant GaAs MESFETs. Experiments and numerical simulations show that the main contribution to I g (in the range of drain biases studied) comes from impact-ionization-generated holes collected at the gate electrode, and that the bell shape of the I g(V gs) curve is strongly related to the drop of the electric field in the channel of the device as V gs is moved towards positive values 相似文献
7.
Busta H.H. Zimmerman B.J. Tringides M.C. Spindt C.A. 《Electron Devices, IEEE Transactions on》1991,38(11):2558-2562
A simple model that is applicable to Spindt-type emitter triodes is presented. Experimentally, it has been observed that the gate current at zero collector voltage follows the same Fowler-Nordheim law as the collector current at high collector voltage, and that for low emission current densities, the sum of gate and collector currents is constant for any collector voltage and is given by the Fowler-Nordheim current I FN. Based on these observations, a simple model has been developed to calculate the I -V characteristics of a triode. By measuring the Fowler-Nordheim emission, emission area and field enhancement can be obtained assuming a value for the barrier height. Incorporating the gate current, the collector current can be calculated from I c=I FN-I g as a function of collector voltage. The model's accuracy is best at low current density. At higher emission currents, deviations occur at low collector voltages because the constancy of gate and collector currents is violated 相似文献
8.
Electrical and reliability characteristics of diagonally shaped n-channel MOSFETs have been extensively investigated. Compared with the conventional device structure, diagonal MOSFETs show longer device lifetime under peak I sub condition (V g =0.5 V d). However, in the high-gate-bias region (V g=V d), diagonal MOSFETs exhibit a significantly higher degradation rate. From the I sub versus gate voltage characteristics, this larger degradation rate under high gate bias is concluded to be due mainly to the current-crowding effect at the drain corner. For a cell-transistor operating condition (V g>V d), this current-crowding effect in the diagonal transistor can be a serious reliability concern 相似文献
9.
Heremans P. Van den Bosch G. Bellens R. Groeseneken G. Maes H.E. 《Electron Devices, IEEE Transactions on》1990,37(4):980-993
The generation of fast interface traps due to channel hot-carrier injection in n-channel MOS transistors is investigated as a function of stress temperature. The relative importance of the mechanisms for the generation of fast interface traps by hot electrons and hot holes is shown to be independent of the temperature. In all cases the generation of fast interface traps is slightly reduced at lower temperatures. The degradation of transistor I d-V g characteristics, on the other hand, is strongly enhanced at lower temperatures. This is explained by a previously suggested model on the temperature dependence of the influence of the local narrow potential barrier, induced at the drain junction as a result of degradation, on the reverse-mode current characteristics. It is shown that only a minor part of the large current reduction at low temperatures can be ascribed to enhanced electron trapping 相似文献
10.
Doyle B.S. Bourcerie M. Bergonzoni C. Benecchi R. Bravis A. Mistry K.R. Boudou A. 《Electron Devices, IEEE Transactions on》1990,37(8):1869-1876
Hot-carrier stressing carried out on conventional and MDD n-MOS transistors under low gate voltage conditions (V g⩽V d/4) is discussed. Following the stress, the devices were subjected to short alternate phases of electron and hole injection into the oxide in order to identify the damage species generated. It is shown that the damage created consists principally of hole and electron oxide traps. This is confirmed using the charge pumping technique. Maximum damage is obtained for conditions of maximum hole injection, indicating that hot holes are responsible for both types of defects. Comparison with maximum interface state damage shows that degradation due to electron traps can be significantly greater than interface state creation in the stressing of n-MOS devices at high drain voltages. The damage is shown to be localized. Two-dimensional simulation of localized charge placed close to the drain junction suggests that equal quantities of positive and negative charge might be created by this stressing. Measurements of capture cross sections for electron trapping reveal two cross sections, σ(1)≈3×10-15 and σ(2)≈3×10-16 cm2 相似文献
11.
Gate oxides grown with partial and complete oxidation in N2 O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g m had a 15×improvement over control oxides not grown in a N2O atmosphere. Further improvement in g m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO2 interface, leading to lower interface state generation (ISG). Improvements were also observed in I g-V g characteristics, indicating a reduction of trap sites both at the Si/SiO2 interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N2O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N 2O oxides and is a subject for further study 相似文献
12.
Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N2O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N2O oxide has significant improvement in t BD (2×under-V g unipolar stress, 20×under+V g unipolar stress, and 10×under bipolar stress). The improvement of t BD in N2O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO2/Si interface 相似文献
13.
A simplified analytical expression for the temperature dependent saturated I D-V D characteristics of hydrogenated amorphous silicon (a-Si:H) thin-film transistors, between -50°C and 90°C, is presented and experimentally verified. The results show that the experimental transfer and output characteristics at several temperatures are easily modeled by a single equation. The model is based on three functions obtained from the experimental data of I D versus V G, over a range of temperature. Theoretical results confirm the simple form of the model in terms of the device geometry. As the temperature increased, the saturated drain current increased and, at a fixed gate voltage the device saturated at increasingly larger drain voltages while the threshold voltage decreased. Good agreement between the measured data and the model was obtained up to 363 K. Also observed at temperatures larger than 363 K was a decrease in I D and more severe gate voltage hysteresis characteristics 相似文献
14.
The looping effect in the I D-V D (drain-current-drain-voltage) characteristics of GaAs MESFETs on semi-insulating substrates has been studied using a two-dimensional numerical analysis. Both the transient and the steady-state behaviors of the looping phenomenon were simulated. Peak voltage- and frequency-dependent behaviors of the looping effect are analyzed. The I D-V D loop is due to the difference in the distribution of ionized EL2 concentration when the drain voltage rises and falls because of the trapping process of EL2s. The output conductance is also found to be frequency-dependent and is explained by the frequency-dependent modulation of the potential barrier height at the channel/substrate interface due to the drain-voltage variation 相似文献
15.
The authors report on the off-state gate current (I g ) characteristics of n-channel MOSFETs using thin nitrided oxide (NO) gate dielectrics prepared by rapid thermal nitridation at 1150°C for 10-300 s. New phenomena observed in NO devices are a significant I g at drain voltages as low as 4 V and an I g injection efficiency reaching 0.8, as compared to 8.5 V and 10-7 in SiO2 devices with gate dielectrics of the same thickness. Based on the drain bias and temperature dependence, it is proposed that I g in MOSFETs with heavily nitrided oxide gate dielectrics arises from hot-hole injection, and the enhancement of gate current injection is due to the lowering of valence-band barrier height for hole emission at the NO/Si interface. The enhanced gate current injection may cause accelerated device degradation in MOSFETs. However, it also presents potential for device applications such as EPROM erasure 相似文献
16.
Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V d=5.5 V and gate voltage V g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG m and threshold voltage shift ΔV t, do not occur at the same V g. As well, ΔK t is very small for the V g <V d stress regime, becomes significant at V g≈V d, and then increases rapidly with increasing V g, whereas ΔG m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress 相似文献
17.
A method of obtaining the spatial distribution of hot-carrier-induced trapped electrons in the gate oxide (N 0t(x )) of PMOSFETs is introduced with the aid of a two-dimensional simulator. The measured I ds versus V ds for various V gs for low drain bias and I ds versus V gs have been compared with data obtained from the simulation concerning the obtained spatial distribution of trapped electrons in the gate oxide. There exists a high degree of agreement between the measured current-voltage characteristics after hot-carrier stress and the simulation results concerning the newly obtained spatial distribution of trapped electrons in the gate oxide 相似文献
18.
Peransin J.-M. Vignaud P. Rigaud D. Vandamme L.K.J. 《Electron Devices, IEEE Transactions on》1990,37(10):2250-2253
The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S I/I 2 versus the effective gate voltage V G=V GS-V off shows three regions which are explained. The observed dependencies are S I/I 2∝V G m with the exponents m =-1, -3, 0 with increasing values of V G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m =0 at large V G or V GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V G , m =-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance 相似文献
19.
Hot-carrier stressing carried out as a function of substrate voltage on 2-μm NMOS devices under bias conditions V d =8 V and V g=5.5 V is discussed. The time power-law dependence of stressing changes as a function of substrate bias (V b), having a power-law gradient of 0.5 for V b=0 V and 0.3 for V b=-9 V. Investigation of the type of damage resulting from stressing shows that at V b=0 V, interface state generation results, while at V b=-9 V, the damage is mostly by charge trapping. Measurements of the gate current under these two substrate bias conditions show that the gate electron current increases by over two orders of magnitude upon application of a strong back bias. It is suggested that the electron trapping arises from this enhanced gate electron current under large substrate voltage conditions 相似文献
20.
Oxide charge buildup during channel-hot-carrier (CHC) injection was investigated by the use of a modified charge-pumping technique. An apparent `turnaround' effect in local oxide charge density during low gate voltage (V T<V g<1/2 V d) stressing was observed. It can be explained by the dynamic evolution of the damage location caused by the continuous changes in the electric field distribution during CHC. Dependence on channel length is also presented 相似文献