改性离子注入高阻SOI衬底的共面波导特性研究

因良好的射频性能,高阻SOI(High-Resistivity Silicon-on-Insulator,HR-SOI)被广泛应用于射频集成电路(RFICs)。通过提取共面波导传输线(Co-Plane Waveguide,CPW)的射频损耗来表征衬底材料的射频性能。高阻SOI衬底由于表面寄生电导效应(Parasitic Surface Conductance,PSC),射频性能恶化。设计并制备了一种新型的改性结构来优化高阻SOI的射频性能,通过将硅离子注入到绝缘埋层中来消除表面寄生电导效应。在0~8 GHz范围内,传输线损耗优于时下业界最先进的TR-SOI的结果(Trap-Rich Layer Silicon-on-Insulator)。由于工艺简单,易于集成化,是极具潜力的射频SOI材料。     

Improved DC and RF performance in Si/SiGe n-MODFETs with ion-implanted buried p-well doping

The dc and RF characteristics of Si/SiGe n-MODFETs with buried p-well doping incorporated by ion implantation are reported. At a drain-to-source biasV/sub ds/ of +1 V devices with 140-nm gate length had peak transconductance g/sub m/ of 450 mS/mm, and maximum dc voltage gain A/sub v/ of 20. These devices also had "off-state" drain current I/sub off/ of 0.15 mA/mm at V/sub g/=-0.5 V. Control devices without p-well doping had A/sub v/=8.1 and I/sub off/=13 mA/mm under the same bias conditions. MODFETs with p-well doping had f/sub T/ as high as 72 GHz at V/sub ds/=+1.2 V. These devices also achieved f/sub T/ of 30 GHz at a drain current, I/sub d/, of only 9.8 mA/mm, compared to I/sub d/=30 mA/mm for previously published MODFETs with no p-well doping and similar peak f/sub T/.     

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28 nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.     

现代通信测试设备必须适合多种手机标准--谈如何选择射频功率分析测试仪器

在通信设备生产领域，射频功率的测量是必不可少的。主信道的功率测量往往决定了接通的质量，邻信道的功率测量则决定不同手机用户之间的干扰程度。而所有上述的指标必须符合相应的工业标准。例如，cdmaOne的手机标准清楚定义了频谱相对于载频的最大干扰度，并指明了有关射频功率测试的详细办法。单纯的功率表往往不能提供与频谱相关的测试功能，因为其不能分辨总功率下的不同子功率，也不能分辨被测发射带宽区域内外的频率。但是，单纯的功率表较为便宜，价格一般为5000美金左右，这对于那些在生产过程中只测量总输出功率的用户来说是符合…     

低噪声低功耗斩波运放的分析与设计

CMOS运放的噪声尤其是低频1/f噪声会随着整体功耗的降低而急剧增加,针对传感器读出电路应用,文中在传统斩波运放的基础上设计了一个低噪声、低功耗的嵌套式斩波运算放大器。基于SMIC0.18 μm工艺,通过Spectre仿真工具进行仿真与验证。高频斩波(fchop,high)频率为500 kHz,低频斩波频率(fchop,low)为2 kHz时的仿真结果表明,运放在100 Hz处的噪声功率谱密度(Power Spectral Density,PSD)降为23 nV[KF(]Hz[KF)],总消耗电流14 μA,放大器的增益带宽积(GBW)为16.7 MHz,运放的电流效率(GBW/Itot)达到了1 193,该设计的整体性能与以往的设计相比具有一定优势。     

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 μm AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz.     

An improved noise loss correction algorithm for learning from noisy labels

Despite excellent performance in image classification researches, the training of the deep neural networks (DNN) needs a large set of clean data with accurate annotations. The collection of a dataset is easy, but annotating the collected data is difficult on the contrary. There are many image data on the websites, which contain inaccurate annotations, but trainings on these datasets may make networks easier to over-fit noisy data and cause performance degradation. In this work, we propose an improved joint optimization framework for noise correction, which uses the Combination of Mix-up entropy and Kullback-Leibler entropy (CMKL) as the loss function. The new loss function can achieve better fine-tuning results after updating all label annotations. The experimental results on publicly available CIFAR-10 dataset and Clothing1M dataset show superior performance of our approach compared with other state-of-the-art methods.     

一种改进的电力线通信系统脉冲噪声抑制方法

为了抑制脉冲噪声对电力线正交频分复用（OFDM）通信系统的影响,最常用的方法之一是在接收端OFDM解调器之前前置一个置零非线性单元,即传统置零法。然而,由于引入了非线性失真,其性能并不理想。针对传统置零法引起的非线性失真问题,提出了一种基于迭代消除非线性失真的改进置零法。首先,对接收到的时域OFDM信号进行脉冲噪声检测和置零处理;然后,在频域利用已检测的符号来重构时域置零处理引入的非线性失真,并通过迭代提高重构的准确性;最后,从频域接收信号中减去重构的非线性失真。仿真结果表明,所提改进算法与传统置零法相比,有非常大的性能提升,增强了电力线OFDM通信系统对脉冲噪声的抵抗能力。     

Comparison of SiC, GaAs, and Si RF MESFET power densities

The maximum power density of Si, GaAs, and 4H-SiC MESFET's was modeled using material parameters, a planar MESFET cross section, and a piecewise linear MESFET drain characteristic. The maximum power density for the Si, GaAs, and 4H-SiC was calculated to be 0.45 W/mm, 0.78 W/mm, and 17.37 W/mm at drain voltages of 8.4 V, 8.3 V, and 105 V, respectively. Modeling power density as a function of drain voltage showed that, for low voltage applications, the GaAs MESFET has the highest power density because of its high electron mobility and very low channel resistance (R_on). For high voltage applications, the 4H-SiC MESFET has the highest absolute power density because of the higher breakdown voltage of this material. Experiment data agree qualitatively with the modeled results     

Mean quantisation noise power for an SPT analogue-to-digitalconverter

The mean quantisation noise power introduced by a signed power-of-two (SPT) analogue-to-digital converter (ADC) is determined. This type of converter approximates an integer (in two's complement format), obtained from an ADC with uniformly distributed quantisation levels, using a signed power-of-two number. The mean quantisation noise power is shown to be strongly dependent on the number of terms used in the signed power-of-two approximation while being largely independent of the two's complement number wordlength     

Selecting an appropriate ESD protection for discrete RF power LDMOSTs

For ESD protections of RF Power MOSTs, V_t1 lowering by the RF signal - due to the dV/dt effect - can seriously degrade the RF performance. The use of a cascoded protection solves this problem. A new failure mechanism, related to the discharge of on-chip RF matching capacitors is presented. Adding a current limiting resistor in the protection solves this issue. Combining these solutions yields an appropriate protection for discrete RF power LDMOSTs.     

Event-driven Simulation and modeling of phase noise of an RF oscillator

A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.     

RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications

In this paper a radio frequency (RF) to direct current (DC) voltage converter with multi-stage rectifiers is reported for micro power conversion in RF power harvesting systems. The purpose of this paper is to select an appropriate structure for the micro power-converters, operating in high frequencies. The main idea is to convert RF range sinusoidal signals to a DC voltage to produce power for the rest of the electrical circuit or a system. The reported rectifier demonstrated an efficiency of 10% at large span of frequency for input signal of 350 mV. In the presented work, an analytical and numerical study of the micro power-converters is reported for various applications. Different design parameters have been investigated for an efficient structure design including, number of MOSs, DC current of a known load, size of MOSFETs capacitors, and frequency of the operation. Consequently, optimized parameters have been reported in order to improve the RF to DC conversion efficiency. Reported circuits were designed and simulated in 180 nm twin-well CMOS process with low threshold metal-oxide semiconductor field-effect transistors (MOSFETS); this multistage rectifier occupied an area of 0.23 mm × 0.146 mm and it produced an output voltage of 2 V at its output. This output voltage can provide the supply voltage required to operate the RFID processing circuitry. Post layout simulations demonstrated that for thirteen stages of the rectifiers, the efficiency of 10% for a capacitive load of 10 pF has been achieved.     

A high quality factor and low power loss micromachined RF bifilar transformer for UWB RFIC applications

In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G/sub Amax/), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF/sub min/) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240/spl times/240 /spl mu/m/sup 2/ after the backside ICP etching. The values of G/sub Amax/ of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications.     

Low power digital TTL command for 1 bit 60 GHz RF MEMS phase shifter

This paper presents a circuit used to actuate Radio Frequency MicroElectroMechanical Systems (RF MEMS) based phase shifters for 60 GHz beam forming. Wireless transmission in the 60 GHz band show a dramatic free space loss, thus making it mandatory to use antennas with high gain in a desired direction. Beam forming is then necessary to optimize the link budget between communicating nodes. Antenna arrays can be used for beam forming. The work done at LAAS was aiming to provide RF MEMS based phase shifters working with a standard digital command. RF MEMS commonly have high actuation voltages usually obtained with charge pumps. This paper presents a full 1 bit phase shifter with a digital translation part, an analog DC–DC converter, and an RF MEMS based loaded line phase shifter for 60 GHz signals. This converter is built using boost converters as an alternative to the use of charge pumps for driving RF MEMS in the field of wireless communications. Boost converters, despite relatively high current peaks, allow shorter settling times compared to charge pumps.     

Integrated antennas on Si with over 100 GHz performance, fabricated using an optimized proton implantation process

We have improved the performance of integrated antennas on Si for possible application in wireless communications and wireless interconnects. For practical VLSI integration, we have reduced the antenna size and optimized the proton implantation to a low energy of /spl sim/4 MeV with a depth of /spl sim/175 /spl mu/m. To avoid any possible contamination, the ion implantation is applied after device fabrication. Excellent performance such as very low RF power loss up to 50 GHz, record high 103 GHz antenna resonance, and sharp 5 GHz bandwidth have been achieved.     

《Test ＆ Measurement World》中文网站开通

随着消费类电子产品的功能不断增加，人们对高性能放大器的要求也越来越苛刻，特别是对放大器的功耗、精确度、噪声比和高速率提出更严格的要求。为应对市场需求，美国国家半导体（NS）公司成功开发出采用全新VIP50工艺技术的6款运算放大器，这些运算放大器无论在准确度、功耗及电压噪音方面都有大幅改善。     

A digitally controlled DC/DC converter for an RF power amplifier

This paper describes design and implementation of a digitally controlled dc/dc converter that provides a dynamically adjustable supply voltage for a radio frequency power amplifier (RFPA). The techniques employed in the design include a combination of constant-frequency continuous conduction mode (CCM) and a variable-frequency discontinuous conduction mode to achieve very high converter efficiency over a wide range of output power levels. The variable-frequency converter control is accomplished using a current-estimator circuit, which eliminates the need for current sensing. A field-programmable gate array (FPGA)-based digital controller implementation allows programmability of the mode transition and other controller parameters. In the complete experimental system, which consists of the digitally controlled dc/dc converter and a class-E RFPA operating at 10GHz, experimental results show that the overall system efficiency is significantly improved over a wide range of RFPA output power levels.     

Performance analysis of a low power low noise tunable band pass filter for multiband RF front end

This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.