A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC

This paper describes a single-chip implementation of a low-voltage image-reject downconverter for a 5.1-5.8-GHz radio receiver. It consists of a low-noise preamplifier (LNA) that is simultaneously noise and power matched to the RF source, and dual doubly balanced mixers coupled to the LNA by a monolithic trifilar transformer. The image-reject architecture eliminates an RF filter, thereby simplifying packaging requirements. The downconverter realizes over 36 dB of image rejection while dissipating 24 mW from a 0.9 V supply, or 18.5 mW at 1.8 V. Conversion gain is 14 dB, IIP3=-5.5 dBm, and noise figure is 6.8 dB (single sideband 50 Ω) when operating from a 0.9 V supply     

A 410-mW 1.22-GHz downconverter in a dual-conversion tuner IC for OpenCable applications

A 1.22-GHz downconverter used in a dual-conversion tuner IC for OpenCable applications is presented. The downconverter is configured as an image-reject receiver and utilizes a trifilar transformer in conjunction with capacitively cross-coupled common-gate mixer input stages to achieve a large dynamic range with relatively low power consumption. Fabricated in a five-metal 0.35-/spl mu/m, 27-GHz f/sub T/, silicon-on-insulator BiCMOS technology and consuming 124 mA from a 3.3-V supply, it downconverts the input to an IF of 44 MHz and achieves 26-dB gain, 23-dB gain control range, 5.1-dB noise figure, 33-dBmV P/sub 1dB/, 56-dBmV IIP/sub 3/, -72-dBc composite triple beat (CTB), -60-dBc cross-modulation, and 30-dB image rejection.     

SiGe bipolar transceiver circuits operating at 60 GHz

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.     

A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver

This paper describes a 0.18-mum CMOS direct-conversion dual-band triple-mode wireless LAN transceiver. The transceiver has a concurrent dual-band low-noise amplifier for low power consumption with a low noise figure, a single widely tunable low-pass filter based on a triode-biased MOSFET transconductor for multi-mode operation with low power consumption, a DC-offset compensation circuit with an adaptive activating feedback loop to achieve a fast response time with low power consumption, and a SigmaDelta-based low-phase-noise fractional-N frequency synthesizer with a switched-resonator voltage controlled oscillator to cover the entire frequency range for the IEEE WLAN standards. The transceiver covers both 2.4-2.5 and 4.9-5.95 GHz and has extremely low power consumption (78 mA in receive mode, 76 mA in transmit mode-both at 2.4/5.2 GHz). A system noise figure of 3.5/4.2 dB, a sensitivity of -93/-94 dBm for a 6-Mb/s OFDM signal, and an error vector magnitude of 3.2/3.4% were obtained at 2.4/5.2 GHz, respectively     

A low-current Ku-band GaAs monolithic image rejectiondown-converter

A single-chip image rejection downconverter has been designed, fabricated. and tested for broadcast satellite receivers operating in the 11.7- to 12.2-GHz range. The downconverter consists of an RF low-noise amplifier (LNA), a filter-type image rejection mixer (IRM), and an intermediate frequency amplifier (IFA). It receives 11.7- to 12.2-GHz RF signals and down converts to 1.0- to 1.5-GHz IF signals with an external local oscillator. Since the filter integrated on the downconverter produces an image rejection of more than 30 dB, the downconverter requires no off-chip circuits for the image rejection. A conversion gain of 37±1 dB and a noise figure of less than 3.5 dB have been achieved over the RF frequency range. The current dissipation is only 40 mA, and the chip size is 2.8 mm×2.8 mm×0.45 mm     

A low-power Ku-band downconverter in InGaP-GaAs HBT technology

We have developed a low-voltage, low-power Ku-band microwave monolithic integrated circuit (MMIC) downconverter using InGaP-GaAs heterojunction bipolar transistor technology. It consists of a preamplifier, a double-balanced mixer, and an L-band wideband intermediate-frequency (IF) amplifier. The downconverter achieves a conversion gain of 31 dB, with a gain flatness within /spl plusmn/ 1 dB, and an output-referred 1-dB compression power (P/sub 1dB,OUT/) of +2.5dBm. This downconverter dissipates 33mA from a 3-V supply. We believe that the operating voltage and power consumption are lower than those of previously published Ku-band MMIC downconverters.     

A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA

This paper describes a 1.5-V low dropout regulator (LDO)-free ultra-low-power 2.4-GHz CMOS receiver for direct-powering through a coin battery. By effective merging the quadrature low noise amplifier (LNA), in phase and quadrature (I/Q) mixers, a voltage controlled oscillator (VCO) and a trans-impedance amplifier (TIA) in one cell, while removing the LDO, we fully utilize the available 1.5-V voltage supply for current-reuse between blocks, minimizing the dc current consumption. Specifically, a quadrature LNA operating as both common-source and common-drain provides the I/Q outputs in the signal path. Forward-body-bias applied to the transconductance stage of the I/Q mixers relaxes their voltage headroom consumption. Prototyped in 180-nm CMOS, the receiver exhibits a conversion gain (CG) of 23 dB, a noise figure (NF) of 13.8 dB and an input-referred 3rd-order intercept point (IIP3) of −14 dBm while consuming only 2 mA. The phase noise of the VCO is −118.5 dBc/Hz at 2.5 MHz offset. The low-cost technology and low current consumption renders the receiver suitable for Internet of Things (IoT) devices using the Bluetooth Low Energy (BLE) or ZigBee standards.     

Design of multistandard adaptive voltage-controlled oscillators

A multistandard/multiband adaptive voltage-controlled oscillator (VCO) satisfying the phase-noise requirements of both second- and third-generation wireless standards is described in this paper (1.8-GHz DCS1800, 2.1-GHz wide-band code division multiple access, and 2.4-GHz wireless local area network, Bluetooth, and digital enhanced cordless telecommunications standards). The design procedure for the VCO is based on an adaptive phase-noise model. A factor of 12 reduction in power consumption with a phase-noise tuning range of 20 dB is demonstrated by adapting the VCO bias to the desired application. The VCO achieves -123-, -110-, and -103-dBc/Hz phase noise at 1-MHz offset in a 2.1-GHz band at supply currents of 6, 1.2, and 0.5 mA, respectively     

一种基于注入锁定环形振荡器的时钟产生电路

提出了一种基于谐波注入锁定数控环形振荡器的时钟产生电路。采用注入锁定技术,极大地抑制了环形振荡器的相位噪声。在频率调谐环路关断的情况下,数控式振荡器可以正常工作,与需要一直工作的锁相环相比,大大节省了功耗。分析了电路的参考杂散性能。在65 nm CMOS工艺下进行流片测试,芯片的面积约为0.2 mm²。测试结果表明,设计的时钟产生电路工作在600 MHz时,1 MHz频偏处的相位噪声为-132 dBc/Hz,在1 V的电源电压下仅消耗了5 mA的电流。     

A Low LO Power Mixer Utilizing the Body Effect

We propose a single-stacked CMOS mixer that can operate at low local oscillator (LO) power condition with a new switching mechanism. Gating the body terminal makes it possible for the mixer to operate in a more ideal switching mode by utilizing the body effect. Biasing at near pinch-off region gives rise to beneficial aspect, low power dissipation. This circuit is composed of all PMOS transistors which draw only 0.275 mA from a supply voltage of 1.8 V. This circuit features gain and noise enhancement characteristic, low power consumption, and simple topology. The proposed mixer achieves conversion gain of 18 dB, noise figure of 9.1 dB with 0 dBm LO power, and power consumption as low as 0.5 mW.     

A low-power oscillator mixer in 0.18-/spl mu/m CMOS technology

A downconversion double-balanced oscillator mixer using 0.18-/spl mu/m CMOS technology is proposed in this paper. This oscillator mixer consists of an individual mixer stacked on a voltage-controlled oscillator (VCO). The stacked structure allows entire mixer current to be reused by the VCO cross-coupled pair to reduce the total current consumption of the individual VCO and mixer. Using individual supply voltages and eliminating the tail current source, the stacked topology requires 1.0-V low supply voltage. The oscillator mixer achieves a voltage conversion gain of 10.9 dB at 4.2-GHz RF frequency. The oscillator mixer exhibits a tuning range of 11.5% and a single-sideband noise figure of 14.5 dB. The dc power consumption is 0.2 mW for the mixer and 2.94 mW for the VCO. This oscillator mixer requires a lower supply voltage and achieves a higher operating frequency among recently reported Si-based self-oscillating mixers and mixer oscillators. The mixer in this oscillator mixer also achieves a low power consumption compared with recently reported low-power mixers.     

基于SiGe HBT工艺的GNSS接收机混频器设计

针对目前国内RFIC发展比较滞后的现状,设计了3款应用于GNSS接收机的基于0．5μm SiGe HBT工艺的混频器（Ⅰ、Ⅱ、Ⅲ）,并采用针对混频器的优良指数FOM（figure—of-merit）对这3个混频器进行结构和综合性能比较。3款混频器的供电电压为3-3V,本振LO输入功率为-10dBm,其消耗总电流、转换增益、噪声系数、1dB增益压缩点依次为：Ⅰ）8．7mA,15dB,4．1dB,-17dBm;Ⅱ）8．4mA,10dB,4．6dB,-10dBm;Ⅲ）5．4mA,11dB,4．9dB,-10dBm。而3款混频器的FOM分别为-57．8、-56．6、-54．3,表明混频器Ⅲ的综合性能最佳,混频器Ⅱ次之,最后为混频器Ⅰ。     

A 5-GHz CMOS wireless LAN receiver front end

This paper presents a 12.4-mW front end for a 5-GHz wireless LAN receiver fabricated in a 0.24-μm CMOS technology. It consists of a low-noise amplifier (LNA), mixers, and an automatically tuned third-order filter controlled by a low-power phase-locked loop. The filter attenuates the image signal by an additional 12 dB beyond what can be achieved by an image-reject architecture. The filter also reduces the noise contribution of the cascode devices in the LNA core. The LNA/filter combination has a noise figure of 4.8 dB, and the overall noise figure of the signal path is 5.2 dB. The overall IIP3 is -2 dBm     

Adaptive multi-standard circuits and systems for wireless communications

Telecom trends such as smooth migration towards higher data rates and higher capacities for multimedia applications, and provision of various services (text, audio, video) from different standards with the same wireless device require integrated designs that work across multiple standards, can easily be reused and achieve maximum hardware share at minimum power consumption. This can be achieved by using adaptive circuits that are able to trade off power consumption for performance on the fly. Realization of the adaptivity function requires scaling of parameters such as current consumption to the demands of the signal-processing task. This paper describes adaptivity design concepts and application of design for adaptivity to multi-standard circuits and systems for wireless communications. An exploratory multi-standard RF front-end is discussed with phase-noise tuning, noise-figure tuning, and input-intercept point tuning requirements of 21 dB, 12 dB, and 7 dB, respectively.     

A 1.57-GHz RF front-end for triple conversion GPS receiver

A low-power, 1.57 GHz RF front-end for a Global Positioning System (GPS) receiver has been designed in a 1.0 μm BiCMOS technology. It consists of a low noise amplifier with 15 dB of gain, a single balanced mixer with 6.3 mS of conversion g_m, a Colpitts LC local oscillator, and an emitter coupled logic (ECL) divide-by-eight prescaler. This front-end has a single sideband (SSB) noise figure of 8.1 dB and is part of a triple conversion superheterodyne receiver whose IF frequencies are 179, 4.7, and 1.05 MHz. Low power consumption has been achieved, with 10.5 mA at 3 V supply voltage for the front-end, while the complete receiver is expected to draw about 12 mA     

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver

A low voltage CMOS RF front-end for IEEE 802.11b WLAN transceiver is presented. The problems to implement the low voltage design and the on-chip input/output impedance matching are considered, and some improved circuits are presented to overcome the problems. Especially, a single-end input, differential output double balanced mixer with an on-chip bias loop is analyzed in detail to show its advantages over other mixers. The transceiver RF front-end has been implemented in 0.18 um CMOS process, the measured results show that the Rx front-end achieves 5.23 dB noise figure, 12.7 dB power gain (50 ohm load), −18 dBm input 1 dB compression point (ICP) and −7 dBm IIP3, and the Tx front-end could output +2.1 dBm power into 50 ohm load with 23.8 dB power gain. The transceiver RF front-end draws 13.6 mA current from a supply voltage of 1.8 V in receive mode and 27.6 mA current in transmit mode. The transceiver RF front-end could satisfy the performance requirements of IEEE802.11b WLAN standard. Supported by the National Natural Science Foundation of China, No. 90407006 and No. 60475018.     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

A four-input beam-forming downconverter for adaptive antennas

A four-input beam-forming downconverter for adaptive antennas is described. It consists of 2-bit variable gain amplifiers (VGAs), 5-bit local oscillator (LO) signal phase shifters using double RC-bridge circuits, and mixers. The VGAs adjust gain deviation between signal paths. A differential-signal-to-eight-phase-signal converter is employed as a part of the LO phase shifter to reduce the chip size. A maximum phase error of 4.1/spl deg/, which is less than 1/2 LSB, is achieved. This error value indicates that the required phase shifter accuracy and the necessary isolation between the VGAs has been achieved. This beam-forming IC is applicable to receivers with adaptive antennas, and is expected to help to reduce the costs of adaptive antenna systems.     

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.     

5-GHz Low Phase-Noise CMOS VCO Integrated With a Micromachined Switchable Differential Inductor

A 5-GHz CMOS voltage-controlled oscillator (VCO) integrated with a micromachined switchable differential inductor is reported in a 0.18 mum radio frequency-CMOS-based microelectromechanical system technology. The power consumption of the core is about 8 mW at the supply voltage of 1.8 V. A total tuning range of 470 MHz (from 5.13 GHz to 5.60 GHz) is achieved as the tuning voltage ranging from 0 V to 1.8 V. In the practical tuning range, the measured phase noise performances at 1 MHz offset are less than -125 dBc/Hz and -126 dBc/Hz when the inductor switch is turned on and off, respectively. The figure-of-merit is better than -190 dB. When compared with a contrast VCO circuit that utilizes a standard switchable differential inductor, this oscillator reaches a phase noise improvement of around 3 dB as the switch is turned on. Around 1-dB on-off phase noise difference can be achievable.