多路反馈型两级交换结构

为解决反馈型两级交换结构中算法可执行时间不足的问题,提出一种多路反馈型两级交换结构MFTS。该结构通过两级crossbar将中间缓存的状态数据反馈到输入端口,输入端口基于处理后的数据提前开始进行算法调度;通过相邻输入端口之间的通信链路使得任一输入端口都能获得邻端口的调度信息,基于该信息和crossbar连接模式的固有特性对调度算法的结果进行终裁,将终裁结果作为最终的算法调度结果。相对于现有方案,MFTS在避免数据包冲突和数据包失序问题的前提下将调度算法可执行时间提高两倍,这使其可支持更大交换规模和更高的端口速率。     

基于ISP1760的USB主机调度器的设计

在一个USB系统中,USB主机管理系统主机与外设的通信传输时,调度器的设计是USB主机驱动设计的主要部分.对嵌入式USB主机控制器而言,主机一般以帧为基础分时调度各传输单元.介绍ISP1760的工作机制,设计基于ISP1760的嵌入式USB主机传输调度器,给出了具体的算法,并成功应用于无线通信终端设备中.     

在CICQ交换结构下实现分布式的输入排队DRR分组公平调度

传统的基于crossbar的输入排队交换结构在提供良好的QoS方面存在很大的不足,而CICQ(combined input and crosspoint buffered queuing)交换结构与传统的交换结构比,不但能在各种输入流下提供接近输出排队的吞吐率,而且能提供良好的QoS支持。基于CICQ结构,提出了在输入排队条件下实现基于流的分布式DRR分组公平调度算法的方案,并通过仿真验证了这一方案的有效性。     

支持多优先级分组交换调度算法研究及其调度器设计

输入缓存交换结构的特点是缓存器和交换结构的运行速率与端口速率相等、实现容易,但存在队头阻塞。如果采用虚拟输出排队方法和适当的分组调度算法可予以消除,使吞吐率达到100%。文章首先研究讨论了并行迭代匹配算法,滑动迭代匹配调度算法的基本原理、迭代仲裁步骤及其硬件实现;对高速分组交换调度算法的性能进行了分析比较。然后给出了在高速输入队列交换机中实现多优先级调度算法的调度器设计与实现方案。经设计实现证明高速分组交换调度算法不仅硬件实现简单,而且具有良好的特性。     

一种基于FPGA实现的高速多路交换开关

多路交换开关是高性能交换部件的核心。本文描述了基于Xilinx公司Virtex-Ⅱ系列FPGA的特点设计和实现的一种高速多路交换开关,它由输入信道组织、内部无阻塞crossba r交换和仲裁调度器三部分组成。仲裁调度器的设计是多路交换开关的关键,申请和仲裁许可的完成时间关系到整个实现的综合频率和性能。我们提出一种改进的行波流水仲
裁器设计,它公平有效,工作频率达到135MHz,在实际应用中效果良好。     

一种高速crossbar调度算法及其性能分析

分析了高速crossbar调度算法iSLIP在处理突发业务时性能严重恶化的原因。结合LQF/iLQF算法的思想,提出了又一种输入排队crossbar调度算法iPGQM。仿真结果表明:该调度算法在均匀业务流量下和iSLIP算法的性能基本相同;在突发业务的条件下,iPGQM算法具有更好的抗突发特性;特别在重负载的条件下,与iSLIP算法相比,不仅具有更高的吞吐量,而且平均延迟降低了10%左右。     

一种维序的基于组合输入输出排队的并行交换结构

提出一种按序排队(in-order queuing,简称IOQ)PPS体系结构,通过在分流控制器引入固定尺寸的缓冲区,实现负载在每个交换平面的均匀分配;中间层组合输入输出排队(combined input-and-output queuing,简称CIOQ)交换平面受控于中央调度器,在每个时间槽(timeslot),中央调度器将同一种匹配实施到每一个交换平面,称之为同步调度策略.可以证明,在该体系结构下,轮询(round robin)分派算法配合同步调度策略可以保证同一条流的信元按序从交换平面读出.进一步提出了严格最长队列优先同步调度算法,极大地减少了中央调度器需要维护的状态信息和信元重定序开销.与目前主流的PPS设计相比,IOQPPS(in-order queuing parallel packet switch)实现机制简单,易于硬件实现.模拟结果表明,IOQPPS具有最优的延迟性能.     

Gigabit交换机中变长分组的时延特性分析

Gigabit交换机能够适应长度可变的各种宽带业务。基于泊松到达和带有输入缓冲的M×N crossbar交换结构提出了一种通用的时延分析方法。通过仿真实验与数值计算结果的比较,证明该方法是切实有效的。     

iRSDRR:一种全异步的基于输入排队Crossbar交换结构的调度算法

DRR(DualRound-Robin)[1]调度算法是一种公平、高效、硬件实现简单的基于输入排队Crossbar交换结构的信元调度算法。为了进一步改善这种算法的性能,该文提出了一种全异步的多次迭代DRR算法,即iRSDRR(iterativeRo-tatingStaticDualRound-Robin)。该算法在开始时,将所有的输入、输出仲裁器的指针全部设置为异步的,以后每个时隙静态地更新所有的仲裁器的指针。仿真结果表明该算法在不同业务流条件下的性能都优于DRR调度算法。     

IPv6中减少ISP交叉流量的结构化P2P流媒体系统

P2P流媒体系统中,减少ISP(Internet Service Provider)交叉流量是一个重要的研究方向,本文提出了一种减少ISP交叉流量的P2P流媒体方案,方案综合考虑了Pull机制、DHT(Distributed Hash Table,分布式哈希表)原理和IPv6地址的聚类特性,从网络拓扑构建和包调度机制两个方面,通过增加ISP内数据共享和减少ISP间数据请求的方式,减少P2P流媒体系统中的ISP交叉流量.仿真结果显示,在大规模系统中,该方案能够有效的减少ISP交叉流量.     

高效的Crossbar仲裁算法--ISP

交换开关是高性能路由器的核心,目前高性能骨干路由器一般采用基于输入队列的ｃｒｏｓｓｂａｒ交换开关。高效的ｃｒｏｓｓｂａｒ仲裁算法对路由器设计十分重要,文中提出一种轮询与Ｒｏｕｎｄ Ｒｏｂｉｎ相结合的仲裁算法－ＩＳＰ（Ｉｎｐｕｔ Ｓｅｒｉａｌ Ｐｏｌｌｉｎｇ）。轻负载时ＩＳＰ算法与ｉＳＬＩＰ算法性能相当,重负载时ＩＳＰ算法在宽带利用率、信元平均延时和公平性等方面优于ｉＳＬＩＰ算法,ＩＳＰ算法实现简单     

Designing and implementing a fast crossbar scheduler

Crossbar switches frequently function as the internal switching fabric of high performance network switches and routers. However, for fairness and high utilization, a crossbar needs an intelligent, centralized scheduler. We describe the design and implementation of a scheduling algorithm for configuring crossbars in input queued switches that support virtual output queues and multiple priority levels of unicast and multicast traffic. We carried out this design for Stanford University's Tiny Tera prototype, a fast, label-swapping packet switch. Its scheduler, designed to configure a crossbar once every 51 ns, implements the ESLIP scheduling algorithm, which consists of multiple round-robin arbiters     

缓冲交叉开关交换结构多播调度算法研究

高性能核心交换设备多播调度受到越来越多的关注·交叉开关结构下的多播调度方案或者性能较差,或者过于复杂,难于应用在高速交换场合·为此,提出一种面向多播的多输入队列缓冲交叉开关体系结构·将多播调度分解为信元分派、输入调度、输出调度3个可分布式并行执行的子问题,并设计了相应的调度算法,降低了算法复杂性·实验结果表明,交叉点缓冲区容量与输入队列数量对多播性能都具有很大的影响·在突发流量到达下,与单多播输入队列的体系结构相比,无论是采用O(1)复杂度的HA-RR-RR还是复杂度更高的调度算法,均能显著提高系统吞吐性能·     

On the Integration of Unicast and Multicast Cell Scheduling in Buffered Crossbar Switches

Internet traffic is a mixture of unicast and multicast flows. Integrated schedulers capable of dealing with both traffic types have been designed mainly for Input Queued (IQ) buffer-less crossbar switches. Combined Input and crossbar queued (CICQ) switches, on the other hand, are known to have better performance than their buffer-less predecessors due to their potential in simplifying the scheduling and improving the switching performance. The design of integrated schedulers in CICQ switches has thus far been neglected. In this paper, we propose a novel CICQ architecture that supports both unicast and multicast traffic along with its appropriate scheduling. In particular, we propose an integrated round-robin-based scheduler that efficiently services both unicast and multicast traffic simultaneously. Our scheme, named multicast and unicast round robin scheduling (MURS), has been shown to outperform all existing schemes under various traffic patterns. Simulation results suggested that we can trade the size of the internal buffers for the number of input multicast queues. We further propose a hardware implementation of our algorithm for a 16 times 16 buffered crossbar switch. The implementation results suggest that MURS can run at 20 Gbps line rate and a clock cycle time of 2.8 ns, reaching an aggregate switching bandwidth of 320 Gbps.     

Practical High-Throughput Crossbar Scheduling

A practical deterministic crossbar scheduler achieves almost full throughput without being heavily affected by short virtual output queues or traffic burstiness. Simple additions offer deterministic service guarantees and distribute the bandwidth of congested links in a weighted, fair manner.     

Design of a crossbar VOQ real-time switch with clock-driven scheduling for a guaranteed delay bound

Most commercial network switches are designed to achieve good average throughput and delay needed for Internet traffic, whereas hard real-time applications demand a bounded delay. Our real-time switch combines clearance-time-optimal switching with clock-based scheduling on a crossbar switching fabric. We use real-time virtual machine tasks to serve both periodic and aperiodic traffic, which simplifies analysis and provides isolation from other system operations. We can then show that any feasible traffic will be switched in two clock periods. This delay bound is enabled by introducing one-shot traffic, which can be constructed at the cost of a fixed delay of one clock period. We carry out simulation to compare our switch with the popular iSLIP crossbar switch scheduler. Our switch has a larger schedulability region, a bounded lower end-to-end switching delay, and a shorter clearance time which is the time required to serve every packet in the system.     

Tiny Tera: a packet switch core

Describes Tiny Tera: a small, high-bandwidth, single-stage switch. Tiny Tera has 32 ports switching fixed-size packets, each operating at over 10 Gbps (approximately the Sonet OC-192e rate, a telecom standard for system interconnects). The switch distinguishes four classes of traffic and includes efficient support for multicasting. We aim to demonstrate that it is possible to use currently available CMOS technology to build this compact switch with an aggregate bandwidth of approximately 1 terabit per second and a central hub no larger than a can of soda. Such a switch could serve as a core for an ATM switch or an Internet router. Tiny Tera is an input-buffered switch, which makes it the highest bandwidth switch possible given a particular CMOS and memory technology. The switch consists of three logical elements: ports, a central crossbar switch, and a central scheduler. It queues packets at a port on entry and optionally prior to exit. The scheduler, which has a map of each port's queue occupancy, determines the crossbar configuration every packet time slot. Input queueing, parallelism, and tight integration are the keys to such a high-bandwidth switch. Input queueing reduces the memory bandwidth requirements: When a switch queues packets at the input, the buffer memories need run no faster than the line rate. Thus, there is no need for the speedup required in output-queued switches     

基于蚁群算法的Hadoop资源感知调度器研究

通过研究蚁群算法,针对现有Hadoop调度器的不足,提出一个基于蚁群算法的Hadoop资源感知调度器及其具体实现方案。从而使Hadoop作业调度器可以更有效地对任务进行分配,提高整体架构的作业性能。通过实验证明,利用蚁群算法实现的资源感知调度器在同构环境中虽没有明显改善系统计算速度,但是在异构环境中可以很好提高系统处理任务的性能,降低了运算时间。