Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing

The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard. It is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-time. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 standard-cell library provide an estimate of 100 MHz achievable clock frequency (worst-case), 52 mm² overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main Profile@Layer3 scenes (ITU-R 601).     

MPEG-4运动补偿处理器的VLSI结构设计

针对MPEG-4编解码中运动补偿控制复杂、数据吞吐量大、实现较困难的特点,提出了一种适合MPEG-4的运动补偿硬件实现方案,解决了时序分配、输人输出控制等较难处理的问题。文中的方案已经在Xilinx ISE6．1i集成开发环境下,采用了VHDL进行描述,并使用了电子设计自动化（EDA）工具进行了模拟和验证。仿真和综合结果表明,该处理器逻辑功能完全正确,能满足MPEG-4Core Profiles＆ Level2实时编码要求,可用于MPEG-4的VLSI实现。     

MPEG-4运动补偿的VLSI结构设计

针对MPEG．4解码中运动补偿控制复杂、数据吞吐量大、实现较困难，提出了一种适合MPEG-4的运动补偿硬件实现方案，解决了时序分配、输入输出控制等较难处理的问题。此方案已经在Xilinx ISE6．li集成开发环境下，采用了VHDL进行描述，并使用了电子设计自动化（EDA）工具进行了模拟和验证。仿真和综合结果表明，设计的运动补偿处理器逻辑功能完全正确，而且可以满足MPEG-4 Core Profiles ＆ Level 2的实时编码要求，可用于MPEG-4的VLSI实现。     

MPEG-4概述

从ISO/IEC14496的第一部分MPEG-4系统的体系结构出发,分别对MPEG-4标准中提供的主要工具进行了技术描述,包括对象描述框架、系统解码器模型(SDM)和传输多媒体集成框架(DMIF)、场景的二进制描述(BIFS)、同步层、视频对象和音频对象编码等.最后对MPEG-4系统的特性做出了小结并探讨了该标准的应用前景.     

Syntax friendly and syntax amendment approaches to error resiliency in the MPEG-4 Simple Scalable Profile

This work discusses two approaches to incorporating error resiliency in the Simple Scalable Profile SSP of the ISO/IEC MPEG-4 14496-2 visual standard. As such scalable MPEG-4 is made suitable for deployment in a mobile communication environment. When it was defined in 2000, the syntax of the Simple Scalable Profile (SSP) prohibited the use of the error resiliency tools which were available in the base layer of the MPEG-4 codec. GPRS simulations are employed to illustrate the need for error resiliency in the SSP profile. Two solutions are then proposed based on whether or not bitstream syntax modifications are employed. The first solution is syntax friendly and emulates the use of the Video Packet resiliency tool whilst remaining compliant with standardized decoders. The limitations and constraints of such an approach are then elaborated upon. It is shown that syntax modifications are inevitable. Thus, the second solution proposes the syntax modifications to incorporate the error resiliency tools of the base layer into the enhancement layers of the SSP profile. The new syntax is verified through subjective testing using Multi Media Double Stimulus Continuous Quality Evaluation (MMDSCQE). Subsequently, the new syntax was approved by the ISO/IEC MPEG-4 committee and resulted in a new profile known as the Error Resilient Simple Scalable Profile (ER-SSP). It is shown that minor modifications are required in the Header Extension tool to synchronize the decoding process between the enhancement and the base layer. Thus, it is shown that base layer error resilience tools are equally applicable to the enhancement layer with nominal syntax changes.     

An 80/20-MHz 160-mW multimedia processor integrated with embeddedDRAM, MPEG-4 accelerator and 3-D rendering engine for mobileapplications

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-μm embedded memory logic (EML) technology. Its area is 84 mm², and power consumption is 160 mW when all of the functions are activated     

HDTV接收系统中视频解码的研究与实现

本文简要分析了HDTV接收系统中视频解码的特点与实现方法,介绍了一种HDTV视频解码器的硬件结构及其工作过程。重点讨论了该视频解码器的软件系统结构,主要模块的设计与实现。该视频解码器可对符合MPEG-2 MP@HL的视频流进行解码并兼容多种视频格式的输出。     

MPEG-4视频编码器MacroBlockIP模块的VLSI结构设计

设计了MPEG-4视频编码器中用于处理纹理部分的模块-MacroBlockIP模块。它主要由重复填充、运动补偿、纹理填充、二维DCT／IDCT、量化／反量化和DC／AC预测六个部分组成。文中的方案在Xilinx ISE6．1i集成开发环境下用VHDL语言进行描述,并使用电子设计自动化（EDA）工具进行了模拟和验证。试验结果表明,所设计的MacroBlockIP模块逻辑功能正确,满足MPEG-4 Core Profiles＆Level2的实时编码要求,可用于MPEG4视频编码器的VLSI实现。     

A 125 μW , Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications

A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18mum one-poly six-metal CMOS technology with an area of 15.21 mm². For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 muW and 108 muW, respectively, at 1V supply voltage     

Pros and cons of fine granular scalability-based MPEG-2 compressed-domain processing

The pros and cons of FGS-based MPEG-2 video transcoding are examined. An existing solution for elastic storage of media (Barrau, 2002) is reviewed. Its shortfalls in terms of picture drift are identified and addressed by means of proposing a modified transcoding architecture, which is then compared to SNR-based MPEG-2 multilayer transcoding. It is shown that the FGS-based MPEG-2 video transcoder has the advantage of simplified transcoding and decoding architectures. However, the SNR-based MPEG-2 transcoder is shown to produce higher quality reconstructed images with superior rate-distortion performance.     

Architecture of a Memory Manager for an MPEG-2 Video Decoding Circuit

A study of the MPEG-2 video decoding standard in Main Profile @ Main Level has been performed, comparing the different solutions existing for the VLSI implementation of the basic functions (Huffman decoding, IDCT...) included in the standard. Afterwards, a new dynamically configurable architecture is proposed for the memory manager, which is necessary to deal with the large data flow inside the decoder. It is aimed at interfacing the external memory, arbitrating the access requests coming from the different decoding units and allowing generic memory requests through the definition of virtual addresses. It is shown that, by means of a particular data organization, the circuit requires an external memory, which is a 2-MB DRAM in fast page or EDO mode, accessible via a 64-bit bus. The memory manager works at 27 MHz and allows a real-time decoding for MP @ ML bitstreams. It has been synthesized in a 0.8-m two-metal CMOS technology and presents a total area of 5.4 mm2 for 6500 gates.     

Two-dimensional mesh-based visual-object representation forinteractive synthetic/natural digital video

This paper first provides an overview of two-dimensional (2-D) and three-dimensional mesh models for digital video processing. It then introduces 2-D mesh-based modeling of video objects as a compact representation of motion and shape for interactive, synthetic/natural video manipulation, compression, and indexing. The 2-D mesh representation and the mesh geometry and motion compression have been included in the visual tools of the upcoming MPEG-4 standard. Functionalities enabled by 2-D mesh-based visual-object representation include animation of still texture maps, transfiguration of video overlays, video morphing, and shape-and motion-based retrieval of video objects     

Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations

MPEG-4 is a new multimedia standard combining interactivity, object-based natural and synthetic digital video, audio and computer-graphics. For the implementation of the video part of the MPEG-4 standard a high degree of flexibility is required, where the motion estimation requires the highest part of the computational power. Therefore, in this paper fast algorithms for MPEG-4 motion estimation are evaluated in terms of visual quality and computational power requirements for processor based implementations. Due to the object-based nature of MPEG-4 also new VLSI architectures for MPEG-4 motion estimation are required. Therefore known motion estimation architectures are evaluated on their capability of being modified for MPEG-4 support. Based on this evaluation a new dedicated, but flexible MPEG-4 motion estimation architecture targeted for low-power handheld applications is presented, which resulted to be advantageous to processor based implementations by magnitudes of order.     

Face and 2-D mesh animation in MPEG-4

This paper presents an overview of some of the synthetic visual objects supported by MPEG-4 version-1, namely animated faces and animated arbitrary 2D uniform and Delaunay meshes. We discuss both specification and compression of face animation and 2D-mesh animation in MPEG-4. Face animation allows to animate a proprietary face model or a face model downloaded to the decoder. We also address integration of the face animation tool with the text-to-speech interface (TTSI), so that face animation can be driven by text input.     

一种基于SoC的MPEG-4视频解码加速器

实现了一种应用于系统芯片（SoC）的MPEG-4视频解码加速器。该解码器可完成MPEG-4解码中计算量最大的离散余弦变换（IDCT）、反量化（inverse quantization）和运动补偿叠加（reconstruction）。本文通过算法、总线接口、存储器结构以及硬件开销方面的优化,使得在满足MPEG-4实时解码的基础上,加速器占用SoC系统芯片的总线带宽和硬件面积尽量的小,并有利于存储器的复用。经实验验证,本设计可以对MPEG-4简单层（simple profile）实时解码。     

MPEG Reconfigurable Video Coding: From specification to a reconfigurable implementation

This paper demonstrates that it is possible to produce automatic, reconfigurable, and portable implementations of multimedia decoders onto platforms with the help of the MPEG Reconfigurable Video Coding (RVC) standard. MPEG RVC is a new formalism standardized by the MPEG consortium used to specify multimedia decoders. It produces visual representations of decoder reference software, with the help of graphs that connect several coding tools from MPEG standards. The approach developed in this paper draws on Dataflow Process Networks to produce a Minimal and Canonical Representation (MCR) of MPEG RVC specifications. The MCR makes it possible to form automatic and reconfigurable implementations of decoders which can match any actual platforms. The contribution is demonstrated on one case study where a generic decoder needs to process a multimedia content with the help of the RVC specification of the decoder required to process it. The overall approach is tested on two decoders from MPEG, namely MPEG-4 part 2 Simple Profile and MPEG-4 part 10 Constrained Baseline Profile. The results validate the following benefits on the MCR of decoders: compact representation, low overhead induced by its compilation, reconfiguration and multi-core abilities.     

基于纹理图像的MPEG-4运动补偿电路的VLSI设计

在采用外部存储和内部缓存的两级存储方案的基础上,提出了一种基于纹理图像的MPEG-4ASP@L5运动补偿电路的硬件结构,并完成了VLSI设计。针对运动向量的预测算法,在满足实时译码的前提下对电路的内部缓存LM2进行了优化。对于重叠块运动补偿算法,提出了一种有效的双循环替换缓存结构。采用TSMC0.25μm1P5MCMOS工艺,完成了运动补偿电路的VLSI实现,芯片内核面积为1.31mm×1.31mm,最高工作频率150MHz。系统仿真结果表明该电路可在120MHz的频率下对符合ASProfile标准的ITU-R601格式的纹理视频流进行实时运动补偿。     

支持MPEG-4面向对象编码的VLSI模块结构设计

MPEG-4中一个新特性是面向对象编码。为了支持这种特性．MPEG-4标准引入了两种新的算法。重复填充和纹理填充.根据这两种算法的特点,设计了MPEG-4重复填充和纹理填充的VLSI结构。文中的方案在Xilinx ISE6．1i集成开发环境下,采用了VHDL进行了描述,并使用电子设计自动化工具进行了模拟和验证。仿真和综合结果表明,本文设计的VLSI处理器,其逻辑功能完全正确,而且可以在很低的时钟频率下满足MPEG-4 Core Profiles ＆ Level2的实时编码要求,可用于MPEG-4的VLSI实现。     

Error-resilient decoding of context-based adaptive binary arithmetic codes

This paper addresses the problem of error-resilient decoding of bitstreams produced by the CABAC (context-based adaptive binary arithmetic coding) algorithm used in the H.264 video coding standard. The paper describes a maximum a posteriori (MAP) estimation algorithm improving the CABAC decoding performances in the presence of transmission errors. Methods improving the re-synchronization and error detection capabilities of the decoder are then described. A variant of the CABAC algorithm supporting error detection based on a forbidden interval is presented. The performances of the decoding algorithm are first assessed with theoretical sources and by considering different binarization codes. They are compared against those obtained with Exp-Golomb codes and with a transmission chain making use of an error-correcting code. The approach has been integrated in an H.264/MPEG-4 AVC video coder and decoder. The PSNR gains obtained are discussed.     

MPEG-4 Simple Visual Profile编码特性剖析及实现

针对低比特率通信,对MPEG-4 Simple Visual Profile的编码特性进行剖析,并对影响编码速度最大运动估计与运动补偿进行讨论,提出实现MPEG-4 Simple Visual Profile编码模式,通过对待压缩帧数据的定义提出MB码流的构成,为MPEG-4编码器在移动通信设备上的实现建立一个研究的基础平台。