Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

The combined effects of low pressure NH3-annealing and H2 plasma hydrogenation on polysilicon thin-film transistors

The low pressure NH₃-annealing and the H₂ plasma hydrogenation were jointly used to improve the characteristics of polysilicon thin-film transistors (TFT's). It was found that the TFT's after applying the above treatments achieved better subthreshold swings, threshold voltages, field effect mobilities, off currents, and reliability. It is believed that the improvement was due to the gate oxynitride formation and the H₂-plasma had a better passivation effect on the oxynitride     

The effects of fluorine passivation on polysilicon thin-filmtransistors

The fluorine implantation on polysilicon was found to improve the characteristics of polysilicon thin-film transistors (TFT's). The fluorine passivates the trap states within the polysilicon channel, as compared with the H₂-plasma passivation. The fluorine implantation passivates more uniformly both the band tail-states and midgap deep-state, while the H₂-plasma treatment is more effective to passivate deep states than tail states. A fluorine-implanted device can be further improved its performance if an H₂-plasma treatment is applied. In contrast to the H₂ -plasma passivation, the fluorine passivation improves the device hot-carrier immunity. Combining the fluorine passivation and H₂ -plasma passivation, a high performance TFT with a high hot-carrier immunity can be obtained     

The effects of NH3 plasma passivation on polysiliconthin-film transistors

The NH₃ plasma passivation has been performed for the first time on the polycrystalline silicon (poly-Si) thin-film transistors (TFT's). It is found that the TFT's after the NH₃ plasma passivation achieve better device performances, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability as well as thermal stability than the H₂-plasma devices. These improvements were attributed to not only the hydrogen passivation of the grain-boundary dangling bonds, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

Formation of high quality storage capacitor dielectrics by in-siturapid thermal reoxidation of Si3N4 films inN2O ambient

This letter reports on a novel reoxidation technique for SiO₂ /Si₃N₄ (ON) stacked films by using N₂ O as oxidant. Effect of in-situ rapid thermal N₂O reoxidation (RTNO) on the electrical characteristics of thin ON stacked films are studied and compared with those of in-situ rapid thermal. O ₂ reoxidation (RTO). Prior to reoxidation, the Si₃N₄ film was deposited by rapid thermal chemical vapor deposition (RT-CVD) using SiH₄ and NH₃. Results show that RTNO of the Si₃N₄ films significantly improves electrical characteristics of ON stacked films in terms of lower leakage current, suppressed charge trapping, reduced defect density and improved time-dependent-dielectric-breakdown (TDDB), as compared to RTO of the Si₃N₄ films     

Characteristics of polysilicon thin-film transistor with thin-gatedielectric grown by electron cyclotron resonance nitrous oxide plasma

Polysilicon thin-film transistors (poly-Si TFT's) with thin-gate oxide grown by electron cyclotron resonance (ECR) nitrous oxide (N₂ O)-plasma oxidation is presented. ECR N₂O-plasma oxidation successfully incorporates nitrogen atoms at the SiO₂/poly-Si interface, consequently forms a nitrogen-rich layer with Si≡N bonds at a binding energy of 397.8 eV. ECR N₂ O-plasma oxide grown on poly-Si films shows higher breakdown fields than thermal oxide. The fabricated poly-Si TFT's with N₂ O-plasma oxide show better performance than those with ECR O₂ -plasma oxide, which results not only from the smooth interface but also oxygen- and nitrogen-plasma passivation     

Effects of surface pretreatment of polysilicon electrode prior toSi3N4 deposition on the electrical characteristicsof Si3N4 dielectric films

Effects of various surface pretreatments of polysilicon electrode prior to Si₃N₄ deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si₃N₄ films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H₂ -Ar clean, and rapid thermal NH₃-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H₂-Ar clean     

The effects of H2-O2-plasma treatment on thecharacteristics of polysilicon thin-film transistors

The effects of H₂-plasma followed by O₂-plasma treatment on n-channel polysilicon thin-film transistors (TFTs) were investigated. It was found that the H₂-O₂-plasma treatment is more effective in passivating the trap states of polysilicon films than the H₂-plasma or O₂-plasma treatment only. Hence, it is more effective in improving the device performance with regard to subthreshold swing, carrier mobility, and the current ON/OFF ratio. It is also found that thermal annealing of plasma-treated devices increases the deep states but has no effect on the tail states of the devices     

Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

Formation of high quality ultrathin oxide/nitride (ON) stackedcapacitors by in situ multiple rapid thermal processing [DRAMcells]

High quality, ultrathin (<30 Å) SiO₂/Si₃ N₄ (ON) stacked film capacitors have been fabricated by in situ rapid-thermal multiprocessing. Si₃N₄ film was deposited on the RTN-treated poly-Si by rapid-thermal chemical vapor deposition (RTCVD) using SiH₄ and NH₃, followed by in situ low pressure rapid-thermal reoxidation in N₂O (LRTNO) or in O₂ (LRTO) ambient. While the use of low pressure reoxidation suppresses severe oxidation of ultrathin Si₃N₄ film, the use of N₂O-reoxidation significantly improves the quality of ON stacked film, resulting in ultrathin ON stacked film capacitors with excellent electrical properties and reliability     

The degradation of TDDB characteristics of Si02/Si3N4/Si02 stacked films caused by surfaceroughness of Si3N4 films [DRAMs]

The effect of surface roughness of Si₃N₄ films on time-dependent dielectric breakdown (TDDB) characteristics of SiO₂/Si₃N₄/SiO₂ (ONO) stacked films was investigated. The surface roughness of Si₃N ₄ films-was found to become higher with increasing deposition temperature and to cause the degradation of TDDB characteristics of ONO films in DRAMs. A local thinning of ONO films, evaluated from the TDDB characteristics, agreed with the surface roughness measured by atomic force microscopy (AFM) and cross-sectional transmission electron microscopy (XTEM). Dependence of time to breakdown of ONO films on the deposition conditions was interpreted by electric field intensification due to the surface roughness of Si₃N₄ films     

垂直型g-C3N4/p++-Si异质结器件的光电性能

通过旋涂法制备垂直型的g-C₃N₄/p⁺⁺-Si异质结器件,研究该异质结器件的光电特性,探索其在可见和紫外光区的光电响应规律。该器件在零偏压和反偏压下均有明显的光电响应。在-1 V偏压下器件响应度为1.52 mA/W(激光波长532 nm,光强3.82 mW/mm²),响应时间约为0.94 s,光电流开关比为1.03×10³。相比于g-C₃N₄器件,g-C₃N₄/p⁺⁺-Si异质结器件具有更高的光电灵敏度。经过分析,其光电性能的提高是由于g-C₃N₄与Si之间形成了高质量的内建电场,该内建电场有效分离了g-C₃N₄中具有高结合能的激子,从而获得高的光生电流。特别是该器件在零偏压条件下的光电流开关比仍然可达10³以上,响应速度为0.5 s,表明g-C₃N₄/p⁺⁺-Si异质结器件在自供电低噪声光电探测器领域具有很好的应用前景。     

Demonstration of Low-Leakage-Current Low-On-Resistance 600-V 5.5-A GaN/AlGaN HEMT

This letter demonstrates a high-voltage, high-current, and low-leakage-current GaN/AlGaN power HEMT with HfO₂ as the gate dielectric and passivation layer. The device is measured up to 600 V, and the maximum on-state drain current is higher than 5.5 A. Performance of small devices with HfO₂ and Si₃N₄ dielectrics is compared. The electric strength of gate dielectrics is measured for both HfO₂ and Si₃N₄. Devices with HfO₂ show better uniformity and lower leakage current than Si₃N₄ passivated devices. The 5.5-A HfO₂ devices demonstrate very low gate (41 nA/mm) and drain (430 nA/mm) leakage-current density and low on-resistance (6.2 Omegamiddotmm or 2.5 mOmegamiddotcm²).     

Sulfide treated GaAs MISFET's with gate insulator of photo-CVDgrown P3N5 film

Sulfide passivated GaAs MISFET's with the gate insulator of photo-CVD grown P₃N₅ films have been successfully fabricated. The device shows the drain current instability less than 22% for the period of 1.0 s ~1.0×10⁴ s, due to excellent properties of sulfide treated P₃N₅/GaAs interface. The effective electron mobility and extrinsic transconductance of the device are about 1300 cm²/V·sec and 1.33 mS, respectively, at room temperature. To estimate the effects of sulfide treatment on P₃N₅/GaAs interfacial properties, GaAs-MIS diodes are also fabricated     

High efficiency polycrystalline silicon solar cells using lowtemperature PECVD process

Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (~10 nm) of PECVD SiO₂ is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si₃N₄) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si₃N₄. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl₃ gettering, hydrogen rf plasma/PECVD Si₃N₄ and PECVD SiO₂ passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si₃N₄ layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si₃N₄ layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500°C. Low temperature (⩽400°C) annealing of the PECVD Si₃N ₄ provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells     

柠檬酸对CeO2磨料分散稳定性及抛光性能的影响

采用柠檬酸作为pH调节剂和分散剂,针对CeO₂磨料水溶液的分散性差以及浅沟槽隔离(STI)化学机械抛光(CMP)过程中正硅酸乙酯(TEOS)/氮化硅(Si₃N₄)的去除速率选择性难以控制的问题进行了研究。分散实验结果表明,由于柠檬酸可以结合在CeO₂颗粒表面从而极大提高了CeO₂磨料的空间位阻,CeO₂溶液的分散稳定性得到提升,因此,与酒石酸、硝酸和磷酸相比,在CeO₂溶液中使用柠檬酸作为pH调节剂,可以使CeO₂磨料具有更小的粒径和较低的分散度以及使CeO₂溶液具有较高绝对值的Zeta电位。抛光实验结果表明,柠檬酸可以极大抑制Si₃N₄的去除速率,且对TEOS的去除速率影响较小,因此,使用柠檬酸作为pH调节剂和分散剂能实现TEOS/Si₃N₄的高去除速率选择比。同时抛光后TEOS和Si₃N₄薄膜具有良好的表面形貌和低的表面粗糙度。     

Study of etch rate characteristics of SF6/He plasmas byresponse-surface methodology: effects of interelectrode spacing

The characteristics of SF₆/He plasmas which are used to etch Si₃N₄ have been examined with experimental design and modeled empirically by response-surface methodology using a Lam Research Autoetch 480 single-wafer system. The effects of variations of process gas flow rate (20-380 sccm), reactor pressure (300-900 mtorr). RF power (50-450 W at 13.56 MHz), and interelectrode spacing (8-25 mm) on the etch rates of LPCVD (low-pressure chemical vapor deposition) Si₃N₄, thermal SiO₂, and photoresist were examined at 22±2°C. Whereas the etch rate of photoresist increases with interelectrode spacing between 8 and 19 mm and then declines between 19 and 25 mm, the etch rate of Si₃N ₄ increases smoothly from 8 to 25 mm, while the etch rate of thermal SiO₂ shows no dependence on spacing between 8 and 25 mm. The etch rates of all three films decrease with increasing reactor pressure. Contour plots of the response surfaces for etch rate and etch uniformity of Si₃N₄ as a function of spacing and flow rate at constant RF power (250 W) display complex behavior at fixed reactor pressures. A satisfactory balance of etch rate and etch uniformity for Si₃N₄ is predicted at low reactor pressure (~300 mtorr), large electrode spacing (12-25 mm), and moderate process gas flow rates (20-250 sccm)     

Electrical characteristics of B-implanted p-channelMNOS transistors

Boron ions (¹¹B⁺ of 3·7 to 7·4 × 10¹¹/cm² were implanted at 60–120 keV into the channel region of p-channel MNOS double layer insulated gate field effect transistors through 920–940 Å of SiO₂ and various thicknesses (300–1800 Å) of Si₃N₄ deposited on SiO₂. Subsequent annealing was performed in a nitrogen atmosphere at 1000°C for 30 min. Acceleration energy, implant dose and Si₃N₄ thickness dependences of the shift of the threshold voltage showed good agreement with the calculated results based on Ishiwara and Furukawa's theory for distribution of implanted atoms in the double layered substrate, using the projected ranges and standard deviations larger than LSS predictions by the factor of 1·2 for SiO₂ and 1·3 for Si₃N₄, respectively. The results on the gain terms and the breakdown voltages were qualitatively the same as those of ¹¹B⁺-implanted p-channel MOS transistors.