多晶硅薄膜晶体管自加热效应温度分布的有限元模拟

采用有限元方法模拟了n型MILC低温多晶硅薄膜晶体管在直流自加热应力下器件的温度分布.通过对器件沟道温度分布的稳态及瞬态模拟,研究了器件功率密度、衬底材料类型和器件宽长等关键因素的影响.确认了改善器件自加热退化的有效途径,同时有助于揭示多晶硅薄膜晶体管自加热退化的内在机制.     

多晶硅薄膜晶体管器件退化机制研究进展

结合近几年来国际上对于低温多晶硅薄膜晶体管器件可靠性开展的一些有代表性的研究工作,对其中几种常见的退化现象;自加热、热载流子和负偏置温度不稳定性做了分析和归纳,介绍了其退化机制及退化模型,并总结了它们在一般情况下对器件性能的影响及各自的典型应力条件。本文针对目前研究较多的自加热退化和热载流子退化机制做了更深入的探讨,比较了两者的差别,并介绍了它们在反转模式下出现的退化恢复现象。此外,文中还介绍了交流应力下的热载流子退化现象,以及在一些特殊器件结构中的退化现象。     

多晶硅TFT热载流子效应的模拟研究

热载流子效应引起的器件电学特性退化会严重影响电路的工作性能。文章结合多晶硅薄膜晶体管沟道电流的理论模型,讨论了热载流子效应与界面陷阱的关系。沟道载流子在大的漏电场牵引下,运动到漏结附近获得很大的能量从而成为热载流子。如果热载流子能量超过Si-SiO2界面势垒高度,会注入到栅氧层或陷落到界面陷阱,使阈值电压和沟道电流发生退化现象。同时,对多晶硅薄膜晶体管输出特性进行了模拟分析,模拟结果与理论模型基本一致。     

搭桥晶粒多晶硅薄膜晶体管栅交流电应力下的退化行为与退化机制研究

本文主要研究了搭桥晶粒(BG)多晶硅薄膜晶体管(TFT)在栅交流电应力下的退化行为和退化机制。在栅交流应力下,动态热载流子效应主导了器件的退化。器件退化只与栅脉冲下降沿有关。越快的下降沿带来越大的动态热载流子退化。比起普通多晶硅TFT,BG多晶硅TFT的热载流子退化大幅度减弱。通过选择性的掺杂注入BG线,沟道中形成的PN结在反向偏置时可以有效分担栅交流电应力带来的电压差,从而减弱动态热载子退化。辅以瞬态模拟结果,栅交流电应力下的退化机制被阐明。所有的测试结果都表明这种高性能高可靠性的BG多晶硅TFT在片上系统应用中具有很大的应用前景。     

高性能金属诱导单向横向晶化多晶硅薄膜晶体管技术和应用

低温金属单向诱导横向晶化多晶硅薄膜晶体管技术与常规的固相晶化多晶硅薄膜晶体管相比，制作工艺简单，而且提高了场效应迁移率和漏极击穿电压，降低了漏电电流，改进了器件参数空间分布的均匀性。我们使用金属单向诱导横向晶化多晶硅薄膜晶体管技术，成功地制作了有源矩阵液晶显示器和有源矩阵有机发光二极管显示器。     

搭桥晶粒多晶硅薄膜晶体管直流电应力下的退化行为与退化机制研究

研究了搭桥晶粒(BG)多晶硅薄膜晶体管(TFT)在直流电应力下的退化行为和退化机制。与普通多晶硅TFT相比,BG多晶硅TFT展现出更好的直流应力可靠性。主要体现在BG多晶硅TFT拥有更好的直流负偏压温度不稳定性(NBTI)可靠性,更好的直流自加热(SH)可靠性,更好的直流热载流子(HC)可靠性。有源沟道区的BG结构是上述直流应力可靠性提高的主要原因。更好的NBTI的可靠性主要源于沟道内的硼氢键的形成;更好的SH可靠性主要源于在沟道长度方向上更快的焦耳热扩散率;更好的HC可靠性主要源于漏端横向电场(Ex)的减弱。所有的测试结果都表明,这种高性能高可靠性的BG多晶硅TFT在片上系统中具有很大的应用前景。     

多晶硅薄膜晶体管kink效应的建模

从kink效应产生的物理机理出发,介绍了目前国内外研究多晶硅薄膜晶体管kink电流所采用的两种主要方法.一种是基于面电荷的方法,另一种是基于求雪崩倍增因子的方法.kink效应具体表现为器件在饱和区跨导和漏电流的显著增加.在数字电路中,kink效应会引起功耗的增加和开关特性的退化;而在模拟电路中,kink效应将降低最大增益和共模抑制比.因此,多晶硅薄膜晶体管kink效应的研究对液晶显示的发展具有重大意义.     

单栅和双栅多晶硅薄膜晶体管的二维器件仿真

二维器件仿真是揭示半导体器件物理机理的有效途径.首先利用二维器件仿真工具构建单栅和双栅多晶硅薄膜晶体管(TFT),并完整地考虑晶界陷阱态的分布规律,即指数分布的带尾态和禁带中央高斯分布的深能态.同时,改变晶界陷阱密度、多晶硅薄膜厚度、温度等条件,以及考虑翘曲(kink)效应,仿真单栅和双栅器件的电流-电压(I-V)特性,分析物理规律,建立对多晶硅TFT器件物理特性的进一步理解.     

微波退火法低温制备多晶硅薄膜晶体管

多晶硅薄膜晶体管以其独特的优点在液晶显示领域中有着重要位置。为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温制备（小于600℃）高质量多晶硅薄膜已成为研究热点,文章利用微波加热技术,采用非晶硅薄膜微波退火固相晶化法低温制备出多晶硅薄膜晶体管,研究了微波退火工艺对多晶硅薄膜晶体管电学性能的影响。     

低温多晶硅薄膜晶体管（p—SiTFT）制作新技术

制作低温多晶硅薄膜晶体管层是制作高性能液晶显示器件技术的一个重要组成部分。本文对制作液晶显示器件的多晶硅薄膜晶体管层工艺及其改进进行了讨论。     

基于有限元法对发射极指分段结构的多指SiGe HBT的研究

针对传统多指SiGe HBT发射极指中心区域和器件中心区域温度较高导致热不稳定问题,提出了新型发射极指分段结构来抑制功率SiGe HBT中心区域的自热效应,提高器件温度分布均匀性.利用有限元软件ANSYS对器件进行建模和三维热模拟,研究器件温度分布的改善情况.结果表明,与传统不分段结构的器件相比,新型分段结构的多指SiGe HBT的指上的温度分布更加均匀、不同指上的温差和集电结结温明显降低,自热效应得到有效抑制,器件的热稳定性得到增强.     

Fabrication and Simulation of Silicon-on-Insulator Structure with Si3N4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3N4 film as a buried insulator (SOSN) are successfully formed using epitaxial layer transfer technology for the first time.The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile.Experiment results show that the buried Si3N4 layer is amorphous and the new SOI material has good structural and electrical properties.The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs.Furthermore,the channel temperature and negative differential resistance are reduced during high-temperature operation,suggesting that SOSN can effectively mitigate the self-heating penalty.The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.     

Temperature stability of a piezoresistive MEMS resonator including self-heating

Temperature stability of a piezoresistive 1.5 μm thin SOI resonator at 74 MHz is presented. As compared to capacitive resonators the self-heating due to the bias current causes a further decrease of the resonator frequency, in addition to the well-known dependency on ambient temperature. The interpretation of the resonance frequency as a device temperature is not obvious anymore under self-heating due to the inhomogeneous temperature distribution.     

SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

Physical modeling of temperature dependences of SOI CMOS devicesand circuits including self-heating

To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature     

以Si3N4为埋层的SOI结构制备与器件模拟

为了减少经典SOI器件的自加热效应,首次成功地用外延方法制备以Si3N4薄膜为埋层的新结构SOSN,用HRTEM和SRP表征了SOI的新结构.实验结果显示,Si3N4层为非晶状态,新结构的SOSN具有良好的结构和电学性能.对传统SOI和新结构SOI的MOSFETs输出电流的输出特性和温度分布用TCAD仿真软件进行了模拟.模拟结果表明,新结构SOSN的MOSFET器件沟道温度和NDR效益都得到很大的降低,表明SOSN能够有效地克服自加热效应和提高MOSFET漏电流.     

Degradation Behaviors of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under DC Bias Stresses

Device degradation behaviors of typical-sized n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors were investigated in detail under two kinds of dc bias stresses: hot-carrier (HC) stress and self-heating (SH) stress. Under HC stress, device degradation is the consequence of HC induced defect generation locally at the drain side. Under a unified model that postulates, the establishment of a potential barrier at the drain side due to carrier transport near trap states, device degradation behavior such as asymmetric on current recovery and threshold voltage degradation can be understood. Under SH stress, a general degradation in subthreshold characteristic was observed. Device degradation is the consequence of deep state generation along the entire channel. Device degradation behaviors were compared in low V_d-stress and in high V_d-stress condition. Defect generation distribution along the channel appears to be different in two cases. In both cases of SH degradation, asymmetric on current recovery was observed. This observation, when in low V_d-stress condition, is tentatively explained by dehydrogenation (hydrogenation) effect at the drain (source) side during stress     

体硅高压LDMOS器件二维温度分布模型

体硅高压LDMOS器件,在不同工作方式下,自身的发热情况也不同.本文通过解热传导方程,研究了体硅N-LDMOS器件准二维温度分布模型.通过该模型,分析了体硅高压N-LDMOS器件工作在线性区与饱和区时温度的分布,器件各个部分自热引起的温度升高以及其在不同宽度的高压脉冲作用下,N-LDMOS器件的温度分布变化情况.     

Thermalelectro-feedback model for multi-emitter finger power heterojunction bipolar transistor. Part I: Temperature profile

Poor thermal conductivity of GaAs, a self-heating phenomenon which results in the rapid rise of device temperature, is the major factor that limits and even degrades the electrical performance of GaAs-based heterojunction bipolar transistor (HBT) operated at high power densities. On the basis of this consideration, a numerical model is presented to study the interaction mechanism between the thermal and electrical behavior of AlGaAs/GaAs HBT with multiple-emitter fingers. The model mainly comprises a numerical model applicable for multi-finger HBT that solves the three-dimensional heat transfer equation. The device design parameters that influence the temperature profile and current distribution of the device are identified, and optimization concerning the device performance is made.