Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs

In this paper, we describe a blind calibration method for gain and timing mismatches in a two-channel time-interleaved low-pass analog-to-digital converters (ADC). The method requires that the input signal should be slightly oversampled. This ensures that there exists a frequency band around the zero frequency where the Fourier transforms of the ADC subchannels are alias free. Low-pass filtering the ADC subchannels to this alias-free band reduces the blind calibration problem to a conventional gain and time delay estimation problem for an unknown signal in noise. An adaptive filtering structure with three fixed FIR filters and two adaptive gain and delay parameters is employed to achieve the calibration. A convergence analysis is presented for the blind calibration technique. Numerical simulations for a bandlimited white noise input and for inputs containing several sinusoidal components demonstrate the effectiveness of the proposed method.     

Toward Wide-Band High-Resolution Analog-to-Digital Converters Using Hybrid Filter Bank Architecture

The paper presents the problem of design and simulation of a high-speed wide-band high-resolution analog-to-digital (ADC) converter working in a bandpass scenario. Such converters play a crucial role in software-defined radio and in cognitive radio technology. One way to circumvent the limits of today’s ADC technologies is to split the analog input signal into multiple components and then sample them with ADCs in parallel. The two main split approaches, time interleaved and frequency splitting, can be modeled using a filter bank paradigm, where each of these two architectures requires a specific analysis for its design. In this research, the frequency splitting approach was implemented with the use of a hybrid filter bank ADC, which requires an output digital filter bank perfectly matched to the input analog filter bank. To achieve this end, an analog transfer function, together with an assumption of strictly band-limited input signal, has been used to design the digital filter bank so far. In contrast, the author proposes dropping the band-limit assumption and shows that the out-of-band input signal has to be taken into account when designing a hybrid filter bank.     

一种并行采样中的自适应非均匀综合校准方法

 并行交替采样中的时间非均匀和幅度非均匀误差严重影响系统性能.本文提出一种基于自适应控制的综合校准方法,同时进行时基、增益和偏置误差的估计,并在估计过程中自动完成校正;采用分数延时滤波器实现时基误差的校正,降低了设计难度与成本.系统校正性能和实时性高,不需要增加额外的校准信号,可以自动跟踪因老化或环境因素导致的误差参数变化.     

Blind Calibration Method for Two-Channel Time-Interleaved Analog-to-Digital Converters Based on FFT

Time-interleaved analog-to-digital(TIADC) is an effective way to improve the sampling rate of an analog-to-digital converter(ADC) system. However, the unavoidable timing mismatch, gain mismatch and offset mismatch significantly degrade the performance of TIADC. In this paper, a blind calibration algorithm based on Fast Fourier Transform Algorithm(FFT) is proposed for the gain, offset and timing mismatches in a two-channel TIADC system. The explicit amplitude relationships between the input signal and the spurs caused by mismatches are derived in the frequency domain. With the explicit amplitude relationships, the frequency component of the input signal, which has the maximal energy, is used to estimate the gain and timing mismatches. The amplitude spectrum of the spur caused by offset mismatch is used to estimate the offset mismatch. The proposed algorithm needs no extra circuits and no training signal and can dynamically track the changes of the mismatches. Simulations show that the estimation errors are no more than 4%. Finally, a two-channel TIADC prototype is used to verify and demonstrate the proposed algorithm.     

Split-ADC based digital background calibration for time-interleaved ADC

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFD) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.     

A Blind RAKE Receiver With Robust Multiuser Interference Cancelation for DS/CDMA Communications

In this paper, a blind RAKE receiver with robust multiuser access interference cancellation is presented for frequency-selective Rayleigh fading channels. In contrast to a conventional receiver, here, only knowledge of the spreading code and rough timing of the desired user is required. By investigating the code space of the multipath signals and the data vector space, a RAKE filtering vector is developed to extract the desired data from all the paths of the desired user. Our proposed technique not only exploits the characteristics of multipath propagation but also the characteristics of timing offsets that may occur in the receiver, to facilitate the application of a blind linear filter-optimization technique for robust interference suppression. Based on the RAKE filtering vector, interference rejection is implemented by using the auxiliary-vector (AV) technique. Our approach, however, effectively overcomes the sensitivity of the original AV method to multipath propagation and timing offsets. To mitigate the signal cancellation at relatively high signal-to-interference and noise ratios (SINR) resulting from the estimation errors of the RAKE filtering vector, robust strategies are introduced in addition to the linear filter optimization. Simulation results are presented to show the effectiveness of the proposed techniques.     

Adaptive MAPSD algorithms for symbol and timing recovery of mobileradio TDMA signals

Dual-mode adaptive algorithms with rapid convergence properties are presented for the equalization of frequency selective fading channels and the recovery of time-division multiple access (TDMA) mobile radio signals. The dual-mode structure consists of an auxiliary adaptive filter that estimates the channel during the training cycle. The converged filter weights are used to initialize a parallel bank of filters that are adapted blindly during the data cycle. When the symbol timing is known, this filter bank generates error residuals that are used to perform approximate maximum a posteriori symbol detection (MAPSD) and provide reliable decisions of the transmitted signal. For channels with timing jitter, joint estimation of the channel parameters and the symbol timing using an extended Kalman filter algorithm is proposed. Various methods are described to reduce the computational complexity of the MAP detector, usually at the cost of some performance degradation. Also, a blind MAPSD algorithm for combining signals from spatially diverse receivers is derived. This diversity MAPSD (DMAPSD) algorithm, which can be easily modified for the dual-mode TDMA application, maintains a global set of MAP metrics even while blindly tracking the individual spatial channels using local error estimates. The performance of these single-channel and diversity MAPSD dual-mode algorithms are studied via computer simulations for various channel models, including a mobile radio channel simulator for the IS-54 digital cellular TDMA standard     

应用于流水线ADC的LMS自适应校准算法与FPGA实现

研究了应用于流水线模数转换器(ADC)的LMS自适应数字校准算法及其FPGA实现。该校准算法可用于校准大多数已知的误差,包括非线性运算放大器的有限增益、电容失配,以及比较器的失调等。通过Simulink软件,对一个12位160 MS/s的流水线ADC进行建模。采用LMS自适应校准算法对该流水线ADC进行校准,并将算法在Virtex-5上实现了硬件设计。实验结果表明, 输入信号频率为58.63 MHz时,流水线ADC的无杂散动态范围(SFDR)和有效位(ENOB)分别由校准前的46.31 dB和7.32位提高到校准后的82.03 dB和11.12位。     

Mixed‐Domain Adaptive Blind Correction of High‐Resolution Time‐Interleaved ADCs

Blind mismatch correction of time‐interleaved analog‐to‐digital converters (TI‐ADC) is a challenging task. We present a practical blind calibration technique for low‐computation, low‐complexity, and high‐resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI‐ADC channels and most real‐life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed‐domain error correction. The proposed technique is experimentally verified by an 400 MSPS TI‐ADC system. In a single‐tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.     

战术数据链空时联合抗干扰技术

针对战术数据链在复杂电磁环境下性能受限的问题,提出基于非标准构型阵列天线的战术数据链空时联合抗干扰技术。该技术在常规导向矢量获取方法失效时,通过设计引导信号,结合盲自适应抗干扰算法进行干扰信号的抑制和引导信号的重构,实现对干扰方向调零抑制并保持通信信号的正常接收。仿真结果表明,通信信号经过空时联合抗干扰处理后,在干扰方向形成的零陷超过-30 dB,大大抑制了干扰方向的信号,保存了信号方向的信号。     

All-digital background calibration technique for timing mismatch of time-interleaved ADCs

An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is further implemented and validated on the Altera FPGA board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of TIADC system.     

Sensitivity of filter bank SCFDMA to carrier frequency offset and its compensation using firefly algorithm

This paper proposes an efficient wireless uplink strategy named filter bank single carrier frequency division multiple access. The proposed system combines the low peak‐to‐average power ratio of precoded orthogonal frequency division multiple access with the reduced out‐of‐band emission of filter bank multicarrier scheme. We present a complete mathematical analysis of the proposed model and derive the conditions to be fulfilled by the transmit filter for perfect data recovery. We further introduce a transmit filter design to enhance the peak‐to‐average power ratio and out‐of‐band emission characteristics of the proposed system. This paper also analyzes the sensitivity of the filter bank single carrier frequency division multiple access system to carrier frequency offset (CFO) and suggests a low complexity interference compensation scheme, under the assumption of perfect knowledge of CFO at the receiver. Later on, the assumption on CFO parameter is removed, and a blind interference compensation technique based on firefly algorithm is developed. Finally, a detailed simulation study is performed to substantiate the effectiveness of the proposed methods.     

分数倍延时数字滤波器设计

在时分交替ADC结构中,由于各子通道ADC采样时钟的偏差,导致通道采样信号误差,严重影响时分交替ADC的动态性能.针对时分交替ADC中子通道的时钟偏差,在信号精确重构的理论依据下,采用基函数分段拟合和频域逼近的方式设计延时低通滤波器.通过改变基函数的定义域,推导了[-Ts,0]内误差校正的理论基础,并结合基函数设计和频...     

调制混合滤波器组的宽带模拟信号采样研究

对于超宽带模拟信号,很难用单个模拟数字转换器（ADC）直接进行采样。该文提出了一种新的并行调制混合滤波器组结构用于实现超宽带模拟信号的采样,首先,将每一路宽带模拟输入信号进行余弦调制,并用相同的低通模拟滤波器均匀分割输入信号的带宽;然后,采用相同的ADC将子带信号数字化;各路子带信号通过上采样器后用数字综合滤波器综合得到原宽带模拟输入信号的数字重构。综合滤波器采用总体最小二乘准则下的特征值滤波器设计方法得到。本文所提出的系统结构不需要使用高速的采样保持电路,降低了系统实现的难度,并且设计的系统具有与其它混合滤波器组相近的重构性能。仿真结果表明了本方法的有效性。      

欠奈奎斯特采样在数字接收机中的应用

从理论上讲，为提高侦察接收机的截获概率，接收机的瞬时带宽必须足够宽。接收机的瞬时带宽决定于接收机的ADC采样速率。因此数字接收机必须具备高速的ADC采样速率。这样对接收机的ADC采样器件性能提出了更高的要求。将采样的方法应用于数字接收机中，可以在一定条件下降低采样速率，同时增加接收机的瞬时带宽。提出了一种基于延时和FFT技术的时域欠采样方法，并在阐述简单原理的基础上找出存在的问题及提出改进方案。重点分析了利用延时和非延时2路通道的相位差与入射信号频率之间的关系，进行信号频率的无模糊估计。基于目前硬件实现水平，数字接收机中采用这种欠采样方法是经济可行的方案。     

基于时延滤波的TI ADC采样时间失配校准算法

针对时间交织型模数转换器(TI ADC)子通道间的采样时间失配,提出了一种基于时延滤波的校准算法。该校准算法是一种纯片外校准算法,在片外进行FFT分析并重新拟合理想信号,提取每个子通道信号的时延偏差,再由此偏差计算每个子通道对应的FIR滤波器系数,完成时延偏差的补偿。该校准算法解决了子通道间采样时间失配导致的TI ADC精度不足的问题。将该算法应用于12 GS/s 12 bit ADC交织板。结果表明,无杂散动态范围(SFDR)平均提升了31.356 4 dBc,有效位数(ENOB)平均提升了3.177 6 bit。     

A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC

This paper presents a split-based feedforward calibration technique for timing mismatch of Time-Interleaved Analog-to-Digital Converter (TI-ADC). The timing mismatch is estimated by using the difference between corresponding sample points of paired split-sub-ADCs, and compensated by a non-derivative interpolation method. Compared with traditional feedback methods with LMS iterative, the proposed feedforward calibration method can achieve much higher calibration speed and the complexity of digital post-processing is greatly relaxed without using of any dummy channel or filters. In addition, it has good calibration effects in both single-tone and multi-tone input conditions. Applied in a 1 GS/s 12-bit TIADC, the simulation result shows a convergence time of 1 × 10⁴Ts under Nyquist frequency input with 2%Ts initial timing mismatch, and the peak signal to noise and distortion ratio of TI-ADC is improved from 37.54 dB to 67.60 dB with a normalized frequency of single-tone input signal f_in/f_S = 0.474. For a multi-tone input signal which contains 10 evenly distributed frequency points in the Nyquist frequency range, after calibration, the signal to noise and distortion improves 28.33 dB.     

Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)

A foreground calibration technique of a pipeline analog-to-digital converter (ADC) has been presented in this paper. This work puts an emphasis on erroneous ADC output occurring due to device mismatch, which, in any standard CMOS process boils down to capacitor mismatch. Deviation of gain of a multiplying digital-to-analog converter (MDAC), also known as the radix of a pipeline ADC stage, from its ideal values adds to the non-linearity of the ADC output. Capacitor mismatch is a major contributor for such an error. The proposed foreground calibration technique makes use of a simple arithmetic unit to extract the radix value from the ADC output for calibration. It uses a sinusoidal signal at the input for calibration purposes. The input sinusoidal signal can be sampled by the ADC clock at any rate for the calibration algorithm to be successful. Behavioral simulation of a pipeline ADC with 5% capacitor mismatch supports the established technique. To verify the calibration algorithm further, pipeline ADCs of different resolutions have been designed and simulated in a 0.18 μm CMOS process.     

Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters

In this paper, a calibration technique for Noise Transfer Function (NTF) optimization of Continuous-Time Bandpass Sigma Delta (CT BP ΣΔ) modulators is presented. The proposed technique employs a test tone applied at the input of the quantizer to evaluate the noise transfer function of the Analog-to-Digital Converter (ADC) using the capabilities of the Digital Signal Processing (DSP) platform usually available in mixed-mode systems. Once the ADC output bit stream is captured, necessary information to generate the control signals to tune the ADC parameters for best Signal-to-Quantization Noise Ratio (SQNR) performance is extracted via an LMS software-based algorithm. Simulation results show that notch frequency of the NTF due to process variations and temperature tolerances can be tuned using the proposed methodology. The proposed global calibration approach can be used during the system start-up and the idle system time. The proposed approach uses a single in-band calibration tone, but it can be expanded using out-of band test tones for background calibration schemes.     

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.