基于SIFT技术的集成电路失效缺陷分析

激励源诱导故障测试(SIFT)是一种新型的失效定位技术,可用于集成电路和分立器件中漏电、击穿、短路等失效点的定位及失效机理的分析。在介绍SIFT技术工作原理的基础上,利用该技术进行了六反相器电路的深埋层缺陷、收发器电路中电源与地之间漏电流失效和串行输出模数转换电路MOS器件欧姆短路的定位,并结合微结构观测分析了失效原因。研究结果表明,SIFT技术能有效分析光发射显微镜(EMMI)和激光光束诱导阻抗变化测试(OBIRCH)技术较难定位的缺陷,弥补了这些常规失效分析技术的不足。     

新型的3D堆叠封装制备工艺及其实验测试

为了满足超大规模集成电路(VLSI)芯片高性能、多功能、小尺寸和低功耗的需求,采用了一种基于贯穿硅通孔(TSV)技术的3D堆叠式封装模型.先用深反应离子刻蚀法(DRIE)形成通孔,然后利用离子化金属电浆(IMP)溅镀法填充通孔,最后用Cu/Sn混合凸点互连芯片和基板,从而形成了3D堆叠式封装的制备工艺样本.对该样本的接触电阻进行了实验测试,结果表明,100 μm2Cu/Sn混合凸点接触电阻约为6.7 mΩ高90 μm的斜通孔电阻在20～30mΩ该模型在高达10 GHz的频率下具有良好的机械和电气性能.     

Screen‐printed Emitter‐Wrap‐Through solar cell with single step side selective emitter with 18.8% efficiency

A fabrication process for Emitter‐Wrap‐Through solar cells on monocrystalline material with high quality gap passivation by wet thermal silicon dioxide is investigated. Masking and structuring steps are performed by screen‐printing technology. Via‐holes are created by an industrially applicable high‐speed laser drilling process. The cell structure features a selective emitter structure fabricated in a single high temperature step: a highly doped emitter at the via‐holes and the rear side, allowing for a low via‐hole resistivity as well as a low resistivity contact to screen‐printed pastes, and a moderately doped front side emitter exhibiting high quantum efficiency in the low wavelength range. Therefore a novel approach is applied depositing either doped or undoped PECVD silicon dioxide layers on the front side. It is shown that doping profiles advantageous for the EWT‐cell structure can be achieved. The screen‐printed aluminum paste is found to penetrate the underlying thermal dioxide layer at appropriate contact firing conditions leading to a zone of high recombination in the overlap region of aluminum and silicon dioxide. It is shown that conventional PECVD‐anti‐reflection silicon nitride acts as effective protection layer reducing the recombination in this region. Designated area conversion efficiencies up to 18.8% on FZ material are obtained applying the single step side selective emitter fabrication technique. Copyright © 2010 John Wiley & Sons, Ltd.     

Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI: Part I—Sources of failures and yield improvement for VLSI

Redundancy of both logic circuits and interconnections is the core principle of both RVLSI (Restructurable or Fault-Tolerant VLSI) and WSI (Wafer Scale Integration). For varying complexity and sizes of circuits different factors of redundancy are required. Effective use of redundancy requires understanding of the failures and failure modes at different stages of the processing and lifetime of VLSI and WSI circuits. This paper consists of two parts. In Part I, sources of failures for MOS devices are discussed. Manifestations of physical failures are described. Use of redundancy for the yield improvement of VLSI circuits is explored through the use of a mathematical model. It is shown that interconnection density and pattern complexities around each section determines the effectiveness of yield improvement. In Part II (to be published in a forthcoming issue), programmable interconnect technologies are described to facilitate restructuring of VLSI and WSI circuits, in this case as they apply to yield improvement through the use of redundancy.     

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.     

阵元失效条件下的高精度DOA估计方法

为解决波达方向（Direction Of Arrival,DOA）估计方法在阵元失效条件下性能下降甚至失效的问题,本文提出一种基于Toeplitz协方差矩阵重构的DOA估计方法.首先,提出了一种失效阵元检测方法,并根据阵列的鲁棒性将失效阵元分为冗余阵元失效和非冗余阵元失效两种情况.然后,分别针对两种失效场景提出相应DOA估计方法：一是冗余阵元失效,利用阵列冗余度,结合差联合阵列对失效阵元进行填充;二是非冗余阵元失效,利用阵列冗余度进行填充后仍存在空洞,结合矩阵填充理论,用迹范数代替秩范数进行凸松弛以恢复协方差矩阵,进而实现对虚拟阵元空洞的填充,恢复阵列自由度.相对于稀疏类算法,有效消除了模型失配的影响.最后,基于子空间方法进行DOA估计.理论和仿真结果表明,相对于现有方法,本文方法有效避免了阵元失效的影响,提高了估计精度.     

Improved SRAM failure diagnosis for process monitoring via current signature analysis

SRAM's are frequently used as monitor circuits for defect related yield, due to the ease of testing and the good correlation to the yield characteristics of logic circuitry. For the identification of the failure/fault type and the nature of the defect causing the failure, measured failbitmaps are mapped onto a failbitmap catalog obtained from defect-fault simulation. Often this mapping is not unique. A given failbitmap can be caused by several faults or defects.In this contribution, the application of current signature analysis is demonstrated for a stand-alone 16kx1 SRAM monitor circuit. It is found that the resolution of the failbitmap-fault-defect catalog can be improved considerably by additional current signature measurements. The interpretation of current measurements is based on simulation of the possible faults contained in the failbitmap catalog under the operating conditions in the current test. There was good agreement between the simulated and measured current values.With the aid of current measurements, more yield learning information is obtained from the process monitoring vehicle. In some cases, the shorted nodes inside a SRAM cell can be determined exactly. This eases the localization of the failure and is of practical importance for the sample preparation in physical failure analysis.     

Effects of contact electrode size on the characteristics of polycrystalline-Si p-i-n solar cells

The effects of contact electrode size on the photo-voltaic characteristics of polycrystalline-Si p-i-n solar cells have been studied,with respect to a unit-cell pitch size of 1μm width.For the non-transparent Al contact electrode with a contact width of 0.05-0.2μm,the short-circuit current is obviously reduced with increasing contact width,due to a larger area of optical reflection by the electrode.On the other hand,even when using a transparent ITO(indium-tin-oxide) electrode,a larger width of contact electrode may also cause a smaller short-circuit current, due to a larger area of optical absorption by the electrode.However,for this ITO electrode,the contact electrode of 0.05μm width causes a smaller short-circuit current than that of 0.1μm width,primarily ascribed to a smaller area for collecting carrier and a larger contact resistance.As a result,while using the ITO contact electrode to enhance the conversion efficiency of the solar cell,a proper width of contact electrode should be employed to optimize the photo-voltaic characteristics.     

Application of Aluminum Oxide to Integrated Circuits Fabrication

Formation characteristics of an aluminum oxide grown by an ``aluminum + water reaction' method are reviewed and its etching rates in some solutions are reported. The aluminum oxide protects the A1 against some chemicals, and serves, by covering the A1 surface with the aluminum oxide, to reduce the frequency of integrated circuit (IC) failures due to aluminum corrosion. Application to epoxy-encapsulated ICs shows that it greatly reduces the frequency of failures in a steam pressure test. Another application to IC chips with gold bumps shows that it drastically reduces the incidence of A1 corrosion which otherwise occurs during bump formation. This method is simple, requires no change in conventional processing, and gave satisfactory results in spite of the presence of glass defects.     

Failure physics of integrated circuits — A review

This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems.In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four groups according to their origin: (i) failure modes associated with chip; (ii) failure modes resulting from leads and bonds; (iii) failure modes associated with encapsulation; and (iv) failure modes due to external effects and overstress. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on failure mode distributions are discussed.In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. Also, the role of electrical testing by the curve tracer and the accompanying analytical techniques (scanning electron microscopy, transmission electron microscopy, electron beam microprobe, Auger electron spectroscopy and X-ray radiograph) are discussed. Finally, the diagnostic technique is described which, using simple electrical testing by the curve tracer and some tests for enhancing of the failure modes (high temperature bake and high temperature burn-in), enables simple detection of integrated circuit failure modes.In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First, the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.     

Fluidic self-assembly for the integration of GaAs light-emittingdiodes on Si substrates

The integration of GaAs optoelectronic devices on Si VLSI is important for many high-bandwidth communication applications. In this paper we describe a novel technique for the quasi-monolithic integration of GaAs light-emitting diodes on Si substrates that utilizes fluid transport and shape differentiation for placement and orientation. GaAs light-emitting diodes fabricated into trapezoidal blocks are suspended in a carrier fluid and deposited over holes etched in Si for integration. Top-side ring contact and bottom electrical contact are fabricated on the blocks prior to integration     

Fault and error models for VLSI

This paper describes a variety of fault and error models which are used as the basis for designing fault-tolerant Very Large Scale Integrated (VLSI) systems. The fault models describe physical defects and failures and the input patterns which will expose them, and are suitable for testing, while error models describe the effects on the functional outputs of defects and are useful for on-line error detection. The models are described at various levels of abstraction. The differences between fault and error models for identical functional modules are also illustrated.     

Characterization of 23-percent efficient silicon solar cells

A silicon solar cell structure, PERC (passivated emitter and rear cell), has very recently demonstrated energy conversion efficiency above 23%. A number of interesting features of the PERC cell design are discussed. Rear contact design is based on a balance between the beneficial effects of small sparsely spaced contact points upon the open circuit voltage and short-circuit current of the cell and the corresponding negative effects upon cell fill factor. The noncontacted regions of the rear surface are held in weak depletion by an optically isolated but electrically connected rear Al reflector. Once bulk injection levels become appreciable, the disadvantage of this surface condition disappears. The structure incorporates a reasonably effective light-trapping scheme, although there remains scope for improvements in this area. Along with other improvements, efficiency approaching 24% seems feasible with the present cell structure. If a processing regime can be found which allows boron passivation of the contact holes or the entire rear surface without loss of the present exceptionally high bulk lifetimes, efficiencies above 24% are likely     

Experimental behavior of single-chip IGBT and COOLMOS devices under repetitive short-circuit conditions

This work presents the behavior of single-chip insulated gate bipolar transistors (IGBT) devices under repetitive short-circuit operations. The 600 and 1200 V nonpunch through IGBTs as well as 600 V COOLMOS (trademark of Infineon Technologies) have been tested. The repetition of these severe working conditions is responsible for devices ageing, and results unavoidably in the components failure. A series of experimental tests were made in order to determine the number of short-circuit operations the devices can support before failure for different dissipated energies. The temperature influence has been also investigated. Results show two distinct failure modes depending on the dissipated energy during the tests. A critical value of short-circuit energy has been pointed out which separates these failure modes. Experimental and numerical investigations have been carried out in order to analyze these failure modes. A detailed analysis of the physical mechanisms occurring during the short-circuit failures for dissipated energies equal or lightly higher than the critical value is presented.     

A 2-ns detecting time, 2-μm CMOS built-in current sensingcircuit

Built-in current testing is known to enhance the defect coverage in CMOS VLSI. An experimental CMOS chip containing a high-speed built-in current sensing (BICS) circuit design is described. This chip has been fabricated through MOSIS 2-μm p-well CMOS technology. The power bus current of an 8×8 parallel multiplier is monitored. This BICS detects all implanted short-circuit defects and some implanted open-circuit defects at a clock speed of 30 MHz (limited by the test setup). SPICE3 simulations indicate a defect detection time of about 2 ns     

MOS multiplier/divider cell for analogue VLSI

A novel all-MOS continuous-time multiplier/divider parameterised cell is introduced. It comprises eight MOS transistors and a single operational amplifier. The new cell is highly reconfigurable, versatile, extremely simple to design and its output its conveniently programmed via DC control voltages. Some of the many applications of the new cell in analogue VLSI signal processing include analogue multiplication, signal squaring, division, signal inversion, amplitude modulation and RMS/DC conversion. Moreover, the new cell is easily extendable to achieve analogue vector multiplication, and hence it lends itself naturally to analogue MOS VLSI implementation of feedback/feedforward neural networks.<>     

引发电控模块短路之PCB孔口发黑原因研究

PCB在使用过程中在经常会出现短路故障,对相关故障电子模块进行分析时发现模块PCB较多孔口存在发黑物质,严重者出现黑色物质连孔,通过测试确认黑色物质具有导电功能。本文通过理论分析及模拟实验论证,确认了黑色物质是引发电子模块故障的根源,同时明确了其产生机理,并提出了针对性的预防措施。     

A fully operational 1-kbit HEMT static RAM

In this paper we describe the current status of materials and fabrication technologies, and optimal design of a memory cell, and the performance of fully functional 1-kbit HEMT SRAM's. The surface defect density on MBE-grown wafers has been reduced to less than 100 cm^-2by improving MBE technology. Standard deviations of threshold voltages are 6.7 and 11.8 mV for enhancement-type and depletion-type HEMT's, respectively, measured in a 10 mm × 10 mm area. These deviations are sufficiently small for DCFL circuits. Memory cell design parameters have been optimized by circuit simulation, where the effects of variations in threshold voltages are taken into account. Full function of 1-kbit SRAM's has been confirmed by marching tests and partial galloping tests. The RAM chips have also shown excellent uniformity in access time. The difference between maximum and average values on the RAM chip is 4 percent.     

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH₄) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.     

Application of selective CVD tungsten for low contact resistance via filling to aluminum multilayer interconnection

Process parameters for selective chemical vapor deposition of tungsten to fill vias between aluminum or aluminum alloy multilevel metallization have been identified and demonstrated. By controlling two competing parallel reactions: Aluminum and hydrogen reductions of tungsten hexafluoride in one reduction step process, the specific contact resistivity was found to be in the range of 2.5 to 8.0 x 10⁻⁹ ohm-cm² for 1.8 micron diameter vias. This is at least one order of magnitude lower than the values reported by the previous workers. It was also observed that alloying the aluminum did not appear to affect the contact resistance significantly. In this experiment one cold wall experimental reactor, two cold wall production systems of two different models and one hot wall tube furnace were used to deposit selective CVD tungsten on aluminum or aluminum with 1% silicon first level metal. As a consequence of these findings, problems associated with filling straight wall vias of high aspect ratio in VLSI multilevel interconnection (i.e., high contact resistance, poor step coverage, electromigration, etc.) can now be alleviated or resolved. Therefore, the use of selective CVD tungsten in the existing aluminum IC metallization becomes very attractive and feasible.