A 622 Mb/s monolithically integrated InGaAs/InP four-channel p-i-nFET receiver array

The authors describe the sensitivity and crosstalk characteristics of a long-wavelength monolithically integrated four-channel photoreceiver array. This receiver consists of 4 p-i-n PDs, 24 JFETs, and 28 level-shift diodes. The device is fabricated using MOVPE-grown crystals and a Be ion implantation technique. The receiver chip demonstrates a sensitivity of between -30.6 and -31.4 dBm, and crosstalk below -20 dB over its operating frequency range. Sensitivity deterioration due to crosstalk is demonstrated and is shown to be a critical factor in system performance. The crosstalk is mainly due to parasitic inductances on the external power supply circuits     

622Mb／s光接收机

本文介绍的光接收机码率为６２２Ｍｂ／ｓ，接收灵敏度为－３１ｄＢｍ、符合ＣＣＩＴＴ关于光同步数字传输网的Ｇ．９５７标准。以此接收机进行了１１０公里的光纤传输试验，连续８小时实测误码为零。     

A 622 Mb/s high-sensitivity monolithic InGaAs-InP pin-FET receiver OEIC employing a cascode preamplifier

A long-wavelength monolithically integrated receiver optoelectronic integrated circuit (OEIC) comprising a low input-capacitance cascode transimpedance preamplifier and a p-i-n photodiode has been demonstrated. The OEIC is fabricated using metal-organic vapor phase epitaxy (MOVPE) grown epilayers and the beryllium ion-implantation technique. The receiver exhibits a sensitivity of -34.7 dBm at 622 Mb/s for BER-10/sup -9/. Using a cascode preamplifier reduces an input capacitance to about one-half of that of an inverter type, which results in the use of a larger feedback resistance of 16 k Omega . The combination of low input capacitance and large feedback resistance reduces the noise current of the receiver and results in high sensitivity.<>     

Miniaturised, hybrid, 500 Mb/s optical receiver package for data-link applications

A clocked, hybrid, 500 Mb/s optical-receiver circuit in a 24-pin package with a ?23 dBm sensitivity, 10?9 b.e.r. and an avalanche gain of 10 is described.     

155/622 Mb/s多发射器激光通信系统

报道一种采用三个发射器、具有自动跟踪功能的无线激光通信系统.描述了系统结构的总体设计、关键的光学、机械和伺服控制单元,包括多个800 nm波段激光发射器,980 nm信标激光发射器,光电接收器,位敏探测器,步进马达和自动跟踪微处理器等.1.3 km的工作距离下的传输实验结果表明,在155 Mb/s的传输速率下,24 h连续运行情况的无误码秒百分比达到98%以上.622 Mb/s传输速率下8 h时统计无误码秒百分比可达95%,平均误码率低于10-9.实验表明多发射器和自动跟踪技术改进了激光无线通信系统的可靠性.     

A 100-channel optical FDM transmission/distribution at 622 Mb/sover 50 km

A 100-channel optical frequency-division multiplexing (FDM) transmission/distribution experiment at 622 Mb/s is demonstrated for a fiber length of 50 km. The feasibility of a polarization-insensitive waveguide frequency selection switch for 10-GHz intervals and a frequency-shift-keying (FSK) direct-detection scheme employing a Mach-Zehnder filter is verified. The demodulation circuit employs a Mach-Zehnder filter and a balanced receiver, which utilizes optical power more efficiently than the Fabry-Perot filter. No receiver sensitivity degradation is observed due to interchannel crosstalk of the 128-channel tunable waveguide frequency selection switch (FS-SW) or fiber four-wave mixing for transmissions over a 50-km-long nondispersion-shifted (NDS) fiber and a 26-km-long dispersion-shifted (DS) fiber     

Design of 622 Mb／s Clock—recovery Monolithic IC for Optical Communication System

A monolithic clock-recovery circuit used in 622Mb/s optical communication system is designed,which is based on the phase-locked loop theory,,and uses bipolar transistor model.It overcomes the shortcoming of clock recovery method based on filter,and implements monolithic clock-recovery IC.The designed circuits include phae detector,voltage-controlled oscillator and loop filter.Among them,the voltage-control oscillator is a modified two-stage ring oscillator,which provides quadrature clock signals and presents wide voltage-controlled range and high voltage-controlling sensitivity.     

A 622 Mb/s LAN/WAN gateway and experiences with wide area ATMnetworking

The use of similar technology in local and wide area networks enables geographically distributed high-performance applications. Key elements in achieving high performance are the appropriate use of traffic control and the development of efficient gateways between LANs and WANs. Even though the basic technology used on both sides of a gateway may be similar, the operational aspects of these elements are significantly different. A gateway has been developed and implemented not only to support communications between an ATM LAN and WAN at 622 Mb/s, but also to provide a platform for conducting network control and traffic research. In addition, the performance of the MAGIC WAN was evaluated, and bottlenecks were identified and analyzed. Techniques were developed and implemented, specifically ATM cell-level pacing, to eliminate these bottlenecks. Throughput performance close to the theoretical maximum was demonstrated. This article describes experiences with ATM over a WAN and how the gateway was developed, implemented, and evaluated. The results included show how high-speed LAN/WAN internetworking can be achieved and applied in many environments as appropriate control techniques and interfaces become ubiquitous     

4×622Mb／s密集波分复用系统280Km光纤传输实验

本文报道４路６２２Ｍｂ／ｓ密集波分复用系统经３级ＥＤＦＡ２８０ｋｍ光纤的传输实验，并对长距离高速密集波分复用系统传输特性进行了分析。     

A 50-Mbit/s CMOS monolithic optical receiver

A general-purpose CMOS optical receiver that operates at data rates from 1 to 50 Mb/s has been fabricated in a 1.75-μm CMOS process. The technology choice resulted in a high level of integration compared with similar bipolar technology receivers. The measured minimum signal current for a 10^-9 bit error rate at 50 Mb/s is 48-nA r.m.s. Automatic gain control gives the receiver an electrical input dynamic range of greater than 60 dB. The outputs are TTL (transistor-transistor logic)-compatible and the chip dissipates less than 500 mW when switching at maximum speed. The die area is 16 mm² . A comprehensive noise analysis of the receiver front end provides insight into the design tradeoffs of optical receiver preamplifiers. A wideband precision amplifier used in the linear channel is discussed in detail. A simple method for recovering low-frequency signal information lost in AC coupling is described     

A 156-Mb/s CMOS optical receiver for burst-mode transmission

In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-μm CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module     

Si-analog IC's for 20 Gb/s optical receiver

Two Si-Analog IC's, a preamplifier IC and a decision IC, for a 20 Gb/s optical receiver have been developed using SiGe-base bipolar transistors having a 60 GHz maximum cutoff frequency. The preamplifier employing a dual feedback loop increases the -3 dB bandwidth up to 19 GHz. A decision IC, composed of a gain controllable amplifier with a bias stabilization circuit and D-F/F, operated at up to 20 Gb/s with a 200-mVp-p input sensitivity     

0.6μm CMOS 622 Mb/s 1∶4分接器芯片设计

采用CSM C-H J 0.6μm CM O S工艺设计,可用于光纤通信系统中工作速率为622 M b/s的1∶4分接器。分析和设计了分接器的系统结构和单元电路,采用Sm artSp ice进行了仿真。整个电路采用5 V单电源供电,功耗为1.1 W。测试工作速率和各项技术指标达到相应标准。     

新型光缓存器和2×622Mb／s ATM光交换系统

本文给出一种新型的光缓存器的结构，以解决在ＡＴＭ光交换中的信元碰撞问题。这种缓存器由光纤延迟线、光波导开关阵及非线性半导体光放大器构成。文中还报告了一种用于交换各用户不同速率的信元（可达６２２Ｍｂ／ｓ）的ＡＴＭ光交换实验系统，系统的总容量为１．２Ｇｂ／ｓ。     

560 Mb/s optical PSK synchronous heterodyne experiment

A phase-locked optical heterodyne receiver constructed using a 1320-nm diode-pumped miniature Nd:YAG ring laser is discussed. Using this receiver and a transmitter based on another Nd:YAG laser, a 560-Mb/s phase-shift keying (PSK) synchronous heterodyne transmission was demonstrated over 78 km of single-mode fiber. With an optical phase-locked loop (PLL) natural frequency of 32 kHz and a damping factor of 1.46, the receiver sensitivity, measured at the output of the transmission link, was -48.7 dBm, or 159 photons/b. The corresponding detected sensitivity, measured on the surface of the p-i-n diode, was -51.8 dBm or 78 photons/b. This result suggests that the receiver sensitivity would have been about 82 photons/b if a balanced receiver with 0.2-dB excess coupler loss had been used. The impact of the finite intermediate frequency (IF) on heterodyne system performance was investigated; it was found that an IF of at least twice the bit rate is needed for a negligibly small penalty     

Dual-channel 1.5 Mb/s lightwave receiver employing an InGaAsP wavelength-demultiplexing detector

A dual-channel 1.5 Mb/s lightwave receiver has been operated simultaneously with optical signals at two different wavelengths. Two individually modulated InGaAsP/InP l.e.d.s provided optical signals at 10 and 1.18 ?m wavelengths, and a new dual-wavelength photodetector served as a demultiplexing detector. The effect of interchannel interference on error rate was measured.     

A CMOS 18 THzΩ 248 Mb/s transimpedance amplifier and 155 Mb/sLED-driver for low cost optical fiber links

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 μm digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is 60 mA which allows a 155 Mb/s optical data-rate. The receiver is a three-stage transimpedance amplifier followed by a signal converter which provides digital output signal levels. The three-stage configuration makes possible the realization of a high transimpedance (150 kΩ), necessary to obtain a high sensitivity, combined with a high bandwidth. The achieved optical data-rate is 240 Mb/s for 1 μA input modulation currents. This results in a transimpedance bandwidth of 18 THzΩ, which is one order of magnitude higher than recently published circuits. The speed performance of the total link is limited by the optical time-constant of the LED, leading to a 155 Mb/s optical link, designed for use in four-fiber interboard connections in 622 Mb/s B-ISDN systems     

All-silicon IC 10 Gb/s optical receiver

A fully integrated 10 Gb/s optical receiver was realized with silicon ICs. The receiver was fabricated on a breadboard utilizing multicarrier assembly. Receiver sensitivity of -29.3 dBm was achieved using an Er-doped optical fiber preamplifier     

用于10Gbit／sSDH光传输系统的光接收机

本文介绍了一种用于１０Ｇｂｉｔ／ｓＳＤＨ光传输系统的光接收机。该接收机的光接口指标可满足ＩＴＵ－ＴＧ．ＳＣＳ建议的要求。已将该接收机用于１０Ｇｂｉｔ／ｓ光纤传输实验。     

A transimpedance APD optical receiver operating at 10 Gb/s

The authors report an optical receiver which uses a separate-absorption-and-multiplication avalanche photodiode (SAM-APD) to achieve high sensitivity at a bit rate of 10 Gb/s. A transimpedance front end incorporating HEMT devices is used for high bandwidth and low noise. The sensitivity (bit-error rate of 10^-9) is -28.7 dBm for a return-to-zero signal, and -27.0 dBm for a nonreturn-to-zero signal