Gallium arsenide [device applications]

The device potential of GaAs and the problems inhibiting its widespread use are examined. Problems encountered in growing wafers are stringent process requirements for obtaining pure material, high susceptibility to lattice defects, small size (2-3 in) of wafers that can be grown, low thermal conductivity necessitating a special heat sink, and the uselessness of native oxide, which must be avoided during manufacture. With respect to the microelectronic properties, the speed of GaAs devices is much higher, with electron velocities measured up to five times that of comparable silicon devices. With very high transconductances and low input capacitances, GaAs devices can obtain much higher gain-bandwidth products (up to 15-20 GHz) that lead to switching speeds of up to 50 ps, about half the speed of silicon. However, this speed advantage erodes at high levels of integration, where costs demand simple and compact packaging. The reasons whey technologies available today for silicon devices-the bipolar junction transistors (BJTs) and field effect transistors (FETs), specifically the MOSFETs-do not work well for GaAs are examined, and new device technologies for GaAs devices-the metal-semiconductor field-effect transistor (MESFET) and the heterojunction bipolar transistor (HBT)-are described     

可关断晶闸管在变频电路中的应用

阐述了可关断晶闸管的特性,普通晶闸管变频电路中存在的问题,在变频电路中采用可关断晶闸管提高变频电路的效率、可靠性等。     

Simulation study of temperature sensitivity of silicon nanowire transistors with different types of orientations

This paper presents the temperature characteristics of a silicon nanowire transistor and its use as a temperature sensor. The OMEN nanowire simulation tool was used to investigate the temperature characteristics of the transistor. Current–voltage characteristics with different values of temperature for three orientations were simulated. The metal–oxide–semiconductor (MOS) diode connection suggests the use of the silicon nanowire transistor as a temperature nanosensor. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Ballistic Transport in SiGe and Strained-Si MOSFETs

We investigate the performance of bulk silicon and strained-silicon nanoscale MOSFETs in the ballistic regime, with the purpose of identifying possible advantages of silicon-germanium technology in devices approaching the ballistic regime. Investigation is performed with a 2D program that solves in a self-consistent way the Poisson equation, the Schrödinger equation with density functional theory, and the continuity equation for ballistic electrons. In the ballistic regime, when mobility has no physical meaning, strained-silicon FETs seem only to provide smaller short channel effects, but no improvement as far as transconductance and drive current are concerned.     

A 0.1 to 2.7‐GHz SOI SP8T antenna switch adopting body self‐adapting bias technique for low‐loss high‐power applications

A low‐loss high‐power single‐pole 8‐throw antenna switch adopting body self‐adapting bias technique in a 0.18‐μm thick‐film partially depleted silicon‐on‐insulator complementary metal‐oxide‐semiconductor process is implemented for multimode multiband cellular applications. A topology with symmetric port design is developed. We employ the body‐contacted field‐effect transistor to handle high power level and obtain low harmonic distortion. However, the conventional bias method for body‐contacted field‐effect transistor leads to poor insertion loss (IL), serious imbalanced voltage division, and large die size. Therefore, a new body self‐adapting bias scheme is adopted to improve the IL and power handling capability with die area reward by removing the employment of extra biasing resistor and voltage supply at the body. The presented silicon‐on‐insulator antenna switch utilizing the new body bias strategy reveals similar harmonic performance as a conventional switch version, thanks to the analogous DC bias to the gate and body, while it exhibits effectively lower IL, imbalanced voltage division, and die area. The measured IL and 0.1‐dB compression point (P_?0.1dB), at 1.9/2.7 GHz, are roughly 0.52/0.82 dB and 39.2/36.9 dBm, respectively. The overall IL and P_?0.1dB are apparently improved by approximately 0.05 to 0.13 dB and 0.5 to 0.8 dBm compared with the conventional version.     

A method for performing fully quantum mechanical simulations of gated silicon quantum wire structures

As transistors get smaller, fully quantum mechanical treatments are required to properly simulate them. Most quantum approaches treat the transport as ballistic, ignoring the scattering that is known to occur in such devices. Here, we review the method we have developed for performing fully quantum mechanical simulations of nanowire transistor devices which incorporates scattering through a real-space self-energy, starting with the assumption that the interactions are weak. The method we have developed is applied to investigate the ballistic to diffusive crossover in a silicon nanowire transistor device.     

高压大功率器件用高温栅偏测试装置研制

为准确评估硅IGBT和碳化硅MOSFET等高压大功率器件不同电应力及热应力条件下的栅极可靠性,研制了实时测量皮安级栅极漏电流的高温栅偏（high temperature gate bias,HTGB）测试装置。此外,该测试装置具备阈值电压在线监测功能,可以更好地监测被测器件的状态以进行可靠性评估和失效分析。为初步验证测试装置的各项功能和可靠性,运用该测试装置对商用IGBT器件在相同温度应力不同电应力条件下进行分组测试。初步测试结果表明老化初期漏电流逐渐降低,最终漏电流大小与电压应力有良好的正相关性,栅偏电压越大,漏电流越大。该测试装置实现了碳化硅MOSFET器件和硅IGBT器件对高温栅偏的测试需求且适用于各种类型的封装。     

Physics-based drain current modeling of gate-all-around junctionless nanowire twin-gate transistor (JN-TGT) for digital applications

Vertically stacked dielectric separated independently controlled gates can be used to realize dual-threshold voltage on a single silicon channel MOS device. This approach significantly reduces the effective layout area and is similar to merging two transistors in series. This multiple independent gate device enables the design of new class of compact logic gates with low power and reduced area. In this paper, we present the junctionless concept based twin gate transistor for digital applications. To analyse the appropriate behaviour of device, this paper presents the modeling, simulation and digital overview of novel gate-all-around junctionless nanowire twin-gate transistor for advanced ultra large scale integration technology. This low power single MOS device gives the full functionality of “AND” gate and can be extended to full functionality of 2-input digital “NAND” gate. To predict accurate behaviour, a physics based analytical drain current model has been developed which also includes the impact of gate depleted source/drain regions. The developed model is verified using ATLAS 3D device simulator. This single channel device can function as “NAND” gate even at low operating voltage.     

高频小功率硅双极晶体管不同管脚端对静电放电失效的机理

在人体模型静电放电（electrostatic discharge,ESD）的注入作用下,部分高频小功率硅双极晶体管对人体模型静电放电最敏感的管脚端对不再是普遍认为的发射极E-基极B间的EB反偏结,而是集电极C与基极B间的CB反偏结。为此,采用微观失效分析与计算机模拟仿真分析相结合的方法,详细讨论了不同管脚对引发典型高频小功率硅双极晶体管ESD失效的效应机理,并针对典型器件内部不同位置的损伤点逐个进行分析。最终得出：高频小功率硅双极晶体管的明显失效往往是由于热二次击穿造成的基极有源区与发射极之间的熔融穿通引起的,而ESD潜在性失效发生的主要原因则是其基极或发射极金属电极附近绝缘介质的场致击穿,从而影响高频小功率硅双极晶体管使用的可靠性。     

MOS Technology Drivers

The semiconductor industry has entered a new revolution where connectivity, applications, and an overall pervasive market drives the need for increased circuit density, improved performance, and a decrease in power dissipation. These issues are the backbone for some of the latest silicon technology advancements, including the integration of stress-enabled transistors and advanced silicon-on-insulator substrates. Future advancements may include multiple gated devices, high- gate oxides, and band-gap-tailored devices. This paper will review some of the early complementary metal-oxide-semiconductor transistor reliability issues and solutions that have allowed this industry to flourish over the last 25 years. A discussion on how these past issues and new advances affect power versus performance is the framework and motivation of this paper.     

基于花朵授粉优化极限学习机的高炉铁水硅含量预测

在高炉冶炼过程中,铁水硅含量是反映高炉炉内温度的重要参数之一,通过对铁水硅含量变化趋势进行预测分析,为后续高炉参数调整提供理论依据。针对铁水硅含量数据的非线性特点,提出基于花朵授粉算法的极限学习机预测方法。利用花朵授粉算法优化极限学习机参数,并通过优化后的极限学习机算法构建铁水硅含量的预测模型,以某钢铁厂生产数据作为验证。仿真结果表明,相较于传统预测方法,该预测模型在预测精度以及泛化能力均有所提高,具有良好的稳定性。     

A Single-Phase Self-Oscillating Thyristor Inverter

A single-phase self-oscillating square-wave inverter using silicon controlled rectifiers, which can operate at any load power factor is described. The inverter can operate either in a fixed-frequency fixed- voltage mode or with a variable-frequency variable-voltage mode within the commutation capability, where the frequency to voltage ratio remains constant. The circuit has higher power handling capability compared to a similar type transistor inverter. A basic center-tapped circuit has been designed and tested and shows promising performance.     

A comparative evaluation of new silicon carbide diodes and state-of-the-art silicon diodes for power electronic applications

Recent progress in silicon carbide (SiC) material has made it feasible to build power devices of reasonable current density. This paper presents results including a comparison with state-of-the-art silicon diodes. Switching losses for two silicon diodes (a fast diode, 600 V, 50 A, 60 ns Trr), an ultrafast silicon diode (600 V, 50 A, 23 ns Trr), and a 4H-SiC diode (600 V, 50 A) are compared. The effect of diode reverse recovery on the turn-on losses of a fast insulated gate bipolar transistor (IGBT) are studied both at room temperature and at 150 /spl deg/C. At room temperature, SiC diodes allow a reduction of IGBT turn-on losses by 25% compared to ultrafast silicon diodes and by 70% compared to fast silicon diodes. At 150 /spl deg/C junction temperature, SiC diodes allow turn-on loss reductions of 35% and 85% compared to ultrafast and fast silicon diodes, respectively. The silicon and SiC diodes are used in a boost converter with the IGBT to assess the overall effect of SiC diodes on the converter characteristics. Efficiency measurements at light load (100 W) and full load (500 W) are reported. Although SiC diodes exhibit very low switching losses, their high conduction losses due to the high forward drop dominate the overall losses, hence reducing the overall efficiency. Since this is an ongoing development, it is expected that future prototypes will have improved forward characteristics.     

SIMULATION OF AMORPHOUS SILICON THIN-FILM TRANSISTOR INCLUDING ADAPTED GUMMEL METHOD

This paper presents an adapted Gummel method (AGM) used in the two-dimensional device simulation of an amorphous-silicon (a-Si) thin-film transistor (TFT). Firstly, the AGM for amorphous silicon is developed by modifying the Gummel method (GM) for crystalline silicon. Secondly, the AGM is implemented into a two-dimensional device simulator for the simulation of a-Si TFTs. The simulation results show that the AGM converges well while the GM fails to converge for the simulation of a-Si TFTs. Hence, the AGM is a useful technique for the simulation and analysis of a-Si TFTs. © 1997 by John Wiley & Sons, Ltd.     

Scalability and process induced variation analysis of polarity controlled silicon nanowire transistor

In this paper, we present scalability and process induced variation analysis of polarity gate silicon nanowire field-effect transistor. 3D simulation results show that the PGFET offers significant reduction in short channel effects and variability due to utilization of uniform lightly doped silicon nanowire (SiNW) as compare to highly doped silicon nanowire in junctionless transistors. The performance parameters were evaluated for different device geometries, such as variation in SiNW radius, equivalent oxide thickness, channel length and spacer length. Sensitivity analysis shows that the PGFET exhibits less dependence towards gate length in comparison to other device parameters. It is seen that ON to OFF current ratio variation with silicon nanowire thickness is lower for PGFET as compared to JLFET. The threshold voltage roll-off and sensitivity towards intrinsic delay in PGFET is much lower than its counterpart device.     

Evaluation of bipolar junction transistor transconductance inpractical applications

The traditional expression that relates the transconductance (g _m) to collector current in a bipolar junction transistor is based upon germanium devices. When this expression is used to estimate performance of modern silicon bipolar-junction transistors (BJTs), significant errors may result. An alternative expression for g_m which is supported by experimental measurements is presented     

Controlling the ON-resistance in SOI LDMOS using parasitic bipolar junction transistor

We present a new parasitic bipolar junction transistor (BJT) enhanced silicon on insulator (SOI) laterally double diffused metal oxide semiconductor (LDMOS), called BJT enhanced LDMOS (BE-LDMOS). The proposed device utilizes the parasitic BJT present in an LDMOS to increase the drain current for a given gate voltage, resulting in a reduction in the ON-resistance by 26.2 % and improving the switching speed by 7.8 % for BE-LDMOS as compared to the comparable LDMOS. These improvements are without degradation in other performance parameters such as off state breakdown voltage and transconductance. The process steps for fabricating BE-LDMOS are same as that for LDMOS except for an additional metal contact.     

All-Optical Modulation in a Silicon Waveguide Based on a Single-Photon Process

All-optical, low-power modulation is a major goal in photonics. Because of their high mode-field concentration and ease of manufacturing, nanoscale silicon waveguides offer an intriguing platform for photonics. So far, all-optical modulators built with silicon photonic circuits have relied on either two-photon absorption or the Kerr effect. Both effects are weak in silicon, and require extremely high (~5 W) peak optical power levels to achieve modulation. Here, we describe an all-optical Mach-Zehnder modulator based on a single-photon absorption (SPA) process, fabricated entirely in silicon. Our SPA modulator is based on a process by which a single photon at 1.55 mum is absorbed and an apparently free-carrier-mediated process causes an index shift in silicon, even though the photon energy does not exceed that of silicon's bandgap. We demonstrate all-optical modulation with a gate response of 1deg/mW at 0.5 Gb/s. This is over an order of magnitude more responsive than typical previously demonstrated devices. Even without resonant enhancement, further engineering may enable all optical modulation with less than 10 mW of gate power required for complete extinction, and speeds of 5 Gb/s or higher.     

A New Concept for Using Ferroelectric Transistors in Nonvolatile Memories

A new concept for using a ferroelectric field effect transistor in a memory configuration is presented without the requirement of a negative voltage or an erase operation. The transistor is designed so that the accumulation sets in at a lower gate source voltage making it possible to reverse the polarization without applying a negative pulse to the gate.     

数显恒温控制器电路设计

用晶体管的PN结作温度传感器,用双向可控硅作无触点控制开关,用ICL7135作A／D转换器等,制作了数显恒温控制器。