An InP/InGaAs p-i-n/HBT monolithic transimpedance photoreceiver

A monolithically integrated 1-Gb/s p-i-n/HBT transimpedance photoreceiver is discussed. The optoelectronic integrated circuit (OEIC) was made from metalorganic vapor-phase epitaxy (MOVPE)-grown InP/InGaAs heterostructures and had a transimpedance of 1375 Ω, a sensitivity of -26.1 dBm, >25-dB dynamic range, and a 500-MHz bandwidth     

Eight-channel p-i-n/HBT monolithic receiver array at 2.5 Gb/s perchannel for WDM applications

We report a monolithic chip incorporating an eight channel p-i-n/HBT photoreceiver array designed for multichannel WDM applications. The p-i-n photodetectors are edge illuminated and centered at a 250 μm pitch for mating with either ribbon fiber connectors or waveguide demultiplexers. Each channel operates at 2.5 Gb/s with an electrical crosstalk of -20 dB between adjacent channels. The average sensitivity of each receiver in the array was measured to be (-20±1) dBm for a bit error rate of 10^-9 at a wavelength of 1.5 μm     

InP-InGaAs single HBT technology for photoreceiver OEIC's at 40Gb/s and beyond

We describe an advanced InP-InGaAs-based technology for the monolithic integration of pin-photodiodes and SHBT-transistors. Both devices are processed using the same epitaxial grown layer structure. Employing this technology, we have designed and fabricated two photoreceivers achieving transimpedance gains of 170 Ω/380 Ω and optical/electrical bandwidths of 50 GHz/34 GHz. To the best of our knowledge, this is the highest bandwidth of any heterojunction bipolar transistor (HBT)-based photoreceiver optoelectronic integrated circuit (OEIC) published to date. We even predict a bandwidth of 60 GHz for the same circuit topology by a simple reduction of the photodiode diameter and an adjustment of the feedback resistor value     

Monolithically integrated InGaAs/InP MSM-FET photoreceiver preparedby chemical beam epitaxy

The first monolithic integration of a metal-semiconductor-metal (MSM) InGaAs photodetector with a field-effect transistor (FET) and resistors into a high-impedance front-end photoreceiver circuit is discussed. The sample was grown in a single step by chemical beam epitaxy, and standard processing steps for making FETs were used to fabricate the receiver circuit. Semi-insulating Fe-doped InP layers were used as the insulating gate of the FET, the barrier enhancement layer in the MSM photodetector, and the electrical isolation layer between the photodetector and the electronic circuit. A bit error rate of less than 10^-9 at 200 Mb/s has been achieved with this preliminary circuit for an optical power of -17 dBm     

A monolithically integrated photoreceiver compatible withInP/InGaAs HBT fabrication process

We demonstrate, for the first time, the characteristics of an InP/InGaAs HBT-compatible pin-PD and a monolithically integrated pin/HBT photoreceiver. The pin-PD can produce a short pulse with an FWHM of 80.8 ps followed by an elongated tail, when illuminated by optical pulses with an FWHM of 40 ps and a wavelength of 1.3 μm. The fall time of the output is determined by the transit time of holes generated in the n ⁺-InGaAs layer. The monolithically integrated photoreceiver, consisting of the pin-PD and a transimpedance preamplifier, can operate at 2.5 Gb/s with a sensitivity of -9.8 dBm. This performance was mainly limited by the characteristics of the pin-PD     

2.5 Gb/s GaAs PIN/PHEMT单片集成光接收机前端

采用0.5 μm GaAs PHEMT工艺,研制了一种PIN光探测器和分布放大器单片集成850 nm光接收机前端. 探测器光敏面直径为30 μm,电容为0.25 pF,10 V反向偏压下的暗电流小于20 nA.分布放大器-3 dB带宽接近20 GHz,跨阻增益约46 dBΩ;在50 MHz～16 GHz范围内,输入、输出电压驻波比均小于2;噪声系数在3.03～6.50 dB之间.单片集成光接收机前端在1.0和2.5 Gb/s非归零(NRZ)伪随机二进制序列(PRBS)调制的光信号下得到较为清晰的输出眼图.     

A novel monolithic HBT-p-i-n-HEMT integrated circuit with HBTactive feedback and p-i-n diode variable gain control

We report the world's first functional MMIC circuit integrating HBT's, HEMT's, and vertical p-i-n diodes on a single III-V substrate. The 1-10 GHz variable gain amplifier monolithically integrates HEMT, HBT, and vertical p-i-n diode devices has been fabricated using selective MBE and a merged processing technology. The VGA offers low-noise figure, wideband gain performance, and good gain flatness over a wide gain control range. A noise figure below 4 dB was achieved using a HEMT transistor for the amplifier stage and a wide bandwidth of 10 GHz. A nominal gain of 10 dB was achieved by incorporating HBT active feedback techniques and 12 dB of gain control range was obtained using a vertical p-i-n diode as a varistor, all integrated into a compact 1.5×0.76 mm² MMIC. The capability of monolithically integrating HBT's, HEMT's, and p-i-n's in a merged process will stimulate the development of new monolithic circuit techniques for achieving optimal performance as well as provide a foundation for high performance mixed-mode multifunctional MMIC chips     

Performance of eight-channel OEIC p-i-n/HBT receiver array in8×2.5 Gb/s WDM transmission system

The performance of an eight-channel, 2.5 Gb/s OEIC photoreceiver array in an eight-wavelength long-distance WDM testbed is described. The sensitivity penalties due to crosstalk and transmission are measured, and the source of crosstalk is investigated. Channel sensitivities range from -25.4 to -26.2 dBm after transmission through 720 km of standard fiber, with transmission penalties ranging from 0.3 dB to 1.0 dB. When the power in each of seven interfering channels is 5 dB above sensitivity, the maximum crosstalk penalty suffered by an individual channel does not exceed 1 dB. These experiments are the first comprehensive characterization of monolithic receiver arrays for crosstalk performance under multichannel operation in a realistic system environment     

A bipolar monolithic multigigabit/s decision circuit

A monolithic multigigabit/s decision circuit using a 0.5-/spl mu/m bipolar process technology called advanced super self-aligned technology (SST-1A) has been developed. A special decision circuit including a novel current switch based on a nonthreshold logic circuit and a cutoff prevention principle was designed and fabricated. An output voltage swing of 1 V across a 50-/spl Omega/ load, a fast transition time of 90 ps (10-90%) and 3.6 Gbit/s operation have been achieved. Power dissipation per chip is about 600 mW. This IC is applicable to very-high-speed optical fiber transmission system repeaters.     

High-speed GaAs SCFL monolithic integrated decision circuit for Gbit/s optical repeaters

A high-speed GaAs monolithic integrated decision circuit for Gbit/s optical repeaters, based on source coupled FET logic (SCFL) and designed to be completely ECL-compatible, has been developed. A clock phase margin of 150 degrees at 2 Gbit/s and IC yields of about 60% are achieved by using SCFL configuration. The developed IC operates stably from 10 to 60°C ambient temperature over a supply voltage fluctuation of more than 2 V.     

10Gb/s突发模式时钟数据恢复电路设计

突发模式的时钟数据恢复是10G EPON系统的关键技术之一。本文介绍了一种基于XNOR/XOR门的振荡器,分析了其工作原理与性能,以此为基础设计了半速率突发时钟恢复电路。设计采用SMIC 0.13?m CMOS工艺进行了流片验证,芯片面积为675?m ? 625?m。测试结果表明,该电路可以即时的实现10Gbit/s的突发数据恢复,恢复出的时钟数据符合IEEE 802.3av标准,锁定时间小于5bit。     

Design, modeling, and characterization of monolithically integratedInP-based (1.55 μm) high-speed (24 Gb/s) p-i-n/HBT front-endphotoreceivers

High-speed, long-wavelength InAlAs/InGaAs OEIC photoreceivers based on a p-i-n/HBT shared layer integration scheme have been designed, fabricated and characterized. The p-i-n photodiodes, formed with the 6000 Å-thick InGaAs precollector layer of the HBT as the absorbing layer, exhibited a responsivity of ~0.4 A/W and a -3 dB optical bandwidth larger than 20 GHz at λ=1.55 μm. The fabricated three-stage transimpedance amplifier with a feedback resistor of 550 Ω demonstrated a transimpedance gain of 46 dBΩ and a -3 dB bandwidth of 20 GHz. The monolithically integrated photoreceiver with a 83 μm p-i-n photodiode consumed a small dc power of 35 mW and demonstrated a measured -3 dB optical bandwidth of 19.5 GHz, which is the highest reported to date for an InAlAs/InGaAs integrated front-end photoreceiver. The OEIC photoreceiver also has a measured input optical dynamic range of 20 dB. The performance of individual devices and integrated circuits was also investigated through detailed CAD-based analysis and characterization. Transient simulations, based on a HSPICE circuit model and previous measurements of eye diagrams for a NRZ 2³¹-1 pseudorandom binary sequence (PRBS), show that the OEIC photoreceiver is capable of operation up to 24 Gb/s     

5-Gbit/s Si integrated regenerative demultiplexer and decision circuit

A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double sampling scheme. Clock phase margin (CPM) and decision ambiguity are 120/spl deg/ and 150 mV at 4 Gb/s, respectively. CPM at 5 Gbit/s is about 90%. Decision feedback equalization may be included in the circuit scheme for optional use.     

A monolithically integrated InGaAs/InP photoreceiver operating witha single 5-V power supply

A monolithic photoreceiver consisting of an InGaAs p-i-n photodiode and a transimpedance preamplifier in which four junction field-effect transistors four level shift diodes, and a feedback resistor are integrated is described. This photoreceiver has been designed to operate with a single 5-V power supply for the purpose of simplifying the whole transmission system. Easily producible device structures were adopted to increase the yield of the photoreceivers. A circuit transimpedance of 965 Ω and a 3-dB frequency of 240 MHz have been obtained for 5-V operation. Transmission of a 400-Mb/s NRZ signal has been achieved     

A 12-Gb/s high-performance, high-sensitivity monolithic p-i-n/HBTphotoreceiver module for long-wavelength transmission systems

A very high sensitivity, high speed, fiber-pigtailed photoreceiver module is described. The OEIC photoreceiver, composed of a p-i-n photodetector monolithically integrated with an InP-InGaAs heterojunction bipolar transistor (HBT)-based transimpedance amplifier, has measured sensitivity of -20 dBm and -17.6 dBm for data rates of 10 and 12 Gb/s, respectively, at a bit error rate of 1×10^-9. These results are the best ever reported for an OEIC photoreceiver at these speeds. In an optical transmission experiment with a low noise erbium-doped fiber amplifier (EDFA) preceding the OEIC photoreceiver, the measured sensitivities were -35.2 and -32 dBm at 10 and 12 Gb/s respectively     

A 10 Gb/s high sensitivity, monolithically integrated p-i-n-HEMToptical receiver

A high-sensitivity, monolithically integrated optical receiver, composed of a p-i-n-PD and high electron mobility transistors (p-i-n-HEMTs) is described. The receiver sensitivity is -17.3 dBm at a bit error rate of 1×10^-9 for a 10-Gb/s non-return-to-zero (NRZ) lightwave signal. This value is the best result yet reported for 10-Gb/s monolithically integrated receivers. The sensitivity is -30.6 dBm if an erbium-doped fiber amplifier (EDFA) is placed ahead of the p-i-n-NEMT receiver. A transmission experiment using a 150-km dispersion-shifted fiber (DSF) indicates no degradation in the bit error rate characteristics or the eye pattern. This verifies the practicality of the p-i-n-HEMT optical receiver for high-speed transmission systems     

A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer

This paper presents the design of a 1 Gb/s 5-tap T/2 fractionally-spaced equalizer. The T/2 delay lines are based on third-order linear-phase double terminated sections that offer a tunable group delay of 500 ps with less than 10% ripple and a 3 dB bandwidth greater than 600 MHz. Furthermore, the equalizer architecture introduces a broadband summing circuit using a transimpedance $I/V$ converter that increases the bandwidth by a factor of 3.6 over a conventional resistive loaded analog adder. The topology's performance is demonstrated in the equalization of 1 Gb/s binary data through CAT5e twisted-pair cables for up to 23 meters. The vertical eye-opening increases from 0% to 58%. Implemented in CMOS 0.35 $mu{hbox{m}}$, the transversal equalizer occupies an area of 26 ${hbox{mm}}^{2}$ and consumes 32 mA.      

A 5 Gb/s CMOS adaptive equalizer for serial link

A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13μm CMOS process.The circuit consists of the combination of equalizer amplifier,limiter amplifier and adaptation loop.The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics.In addition,an offset cancellation loop is used to alleviate the offset influence of the signal path.The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply.Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter.     

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.     

低电压低功耗CMOS 5Gb/s串行收发器

设计并实现了一种使用0.13μm CMOS 工艺制造的低电压低功耗串行收发器.它的核心电路工作电压为1V,工作频率范围为2.5~5GHz.发送器包括一个20:1的串行器和一个发送驱动器,其中发送驱动器采用了预加重技术来抵消传输信道对信号的衰减,降低信号的码间串扰.接收器包括一个输入信号预放大器,两个1:20的解串器以及时钟恢复电路.在输入信号预放大器中设计了一个简单新颖的电路,利用前馈均衡来进一步消除信号的码间串扰,提高接收器的灵敏度.测试表明,收发器功耗为127mW/通道.发送器输出信号均方根抖动为4ps.接收器在输入信号眼图闭合0.5UI,信号差分峰-峰值150mV条件下误码率小于10-12.