Variation of lateral doping as a field terminator for high-voltage power devices

In this brief a new concept for high-voltage planar junctions is presented. The necessary widening of the space-charge region at the junction surface is obtained by implantation through small openings in the oxide mask and subsequent drive-in, leading to a controlled smeared-out dopant distribution. Compared to other planar junctions, this concept also yields a gain in active chip area. Experimental results show the validity of the concept.     

Coupled loops at 20 GHz for stacked planar circuits

Differential planar coupled loops are examined as a method of integrating silicon electronics with passive elements on low-loss microwave laminates. Two test structures are examined which abut planar loops on a CMOS chip to similarly sized loops on a low-loss microwave laminate. The insertion loss of a pair of the 1000times1000 mum loops was measured to be approximately 3 dB at 20 GHz, and the loss between the 700times300 mum loops was measured to be approximately 6 dB at 20 GHz     

基于倒扣技术的24GHz混合集成平衡混频器

介绍采用混合贴装倒扣二极管技术制造的新型24GHz平衡混频器，并对该混频器进行设计、仿真、加工和测试，它能提供中频100kMz时小于10dB的变频损耗，本振与信号之间优于35dB的隔离度，其结构特点利于大批量、低成本生产，适合汽车电子系统的需求。     

Spatially singlemode broad-area semiconductor laser with planar external cavity

A broad-area laser diode combined with a planar external waveguide cavity operates in the fundamental mode and reshapes the output emission into a circular 15/spl deg/ beam. A 500 /spl mu/m-long by 40 /spl mu/m-wide laser diode with uncoated facets coupled with the uncoated ModeReShaper (MRS) planar chip has a coupling efficiency of /spl sim/40% and stabilised the fundamental mode at drive currents up to three-times threshold.     

Planar clock routing for high performance chip and packageco-design

A new concept of chip and package co-design for the clock network is presented in this paper. We propose a two level clock distribution scheme which partitions the clock network into two levels. First, the clock terminals are partitioned into a set of clusters. For each cluster, a local on-chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside this cluster. The clock signal is then distributed from the main clock driver to each of local buffers by means of a global clock tree, which is a planar tree with equal path lengths. With the flip chip area I/O attachment, the planar global clock tree can be put on a dedicated package layer. The interconnect on the package layer has two to four order smaller resistance than that on the chip layer. The main contribution of this paper is a novel algorithm to construct a planar clock tree with equal path lengths-the length of the path from the clock source to each destination is exactly the same. In addition, the path length from the source to destinations is minimized     

芯片级原子钟专用射频模块设计

为进一步实现原子钟的低功耗、微型化,设计了一种用于85Rb原子钟的专用射频模块芯片。该芯片采用了交叉耦合差分结构,利用串联的平面集成螺旋电感达到3 GHz的输出频率,同时采用了累积型MOS变容管,实现控制电压对于输出频率的单调调节。最终对设计芯片进行了仿真测试,并完成了流片与封装,基本达到了设计指标。     

芯片制造的电化学处理技术

电化学处理技术的性价比优势在芯片制造上是一个范例转移。Cu芯片金属化的双大马士革处理和面阵列芯片封装互连的C4(倒装)技术使电化学技术置于最复杂的制造工艺技术之间。这些工艺技术被集成到用于芯片制造的300mm晶圆处理中。新材料和工艺的持续发展来满足微处理器件不断增加性能和小型化的趋势。电迁移问题和集成超低k电介质材料与Cu镀层的新抛光方法是芯片制造中的一个关键问题。发展一个适用成本低的无铅C4芯片封装互连是微电子工业的主要目标,微电子工业正作努力在几年里市场化无铅产品。     

Response Surface Based Optimization Approach for Thermal Placement Design of Chips in Multiple-Chip Modules

This paper attempts to perform thermal enhancement of planar multiple-chip modules (MCMs) containing a number of chips of equal and/or unequal power through optimal chip placement design. To achieve the goal, an effective design approach is presented for the thermal design optimization problems in the context of models of placement of chips in MCMs. The approach combines the use of the currently proposed response surface (RS) based methodology, which is an optimization algorithm and a finite element modeling technique. The proposed RS-based methodology is used for creating a macro mathematical expression of the design objective of the thermal optimization problem, i.e., the total chip junction temperature of the system, associated with the design parameters, including the chip location and power. The validity of the mathematical expressions constructed is verified through two approaches. Furthermore, to make the constructed mathematical expression more compact while maintaining the associated solution accuracy, the backward variable elimination technique is employed. The effectiveness of the proposed design optimization methodology is demonstrated through several design case studies involving planar plastic ball grid array type MCMs. It is found that the proposed RS-based methodology could accurately define the macro mathematical model of the total system chip junction temperature in terms of the chip location and power. In addition, results show that the current optimal chip placement design can provide a minimal system temperature.     

PbS量子点同质P-N结光电探测器

PbS胶体量子点因其带隙可调、可溶液加工、吸收系数高等优异特性而广泛应用于光电探测器领域。然而基于光电二极管结构的PbS量子点光电探测器通常会使用不同的材料来制备N型层,从而增加了器件设计和工艺的复杂性,不利于这类光电探测器未来在面阵成像芯片中的应用。为简化制备工艺,提出了一种PbS量子点同质P-N结光电探测器,仅通过一种工艺过程实现了器件P型层和N型层的制备。经测试,探测器对不同入射光强度的探测表现出了良好的线性响应;在0.5 V反向偏压作用下,器件在700 nm处的响应度为0.11 A/W,比探测率为3.41×1011 Jones,展现出了其对弱光探测的优异能力。结果表明文中提出的PbS量子点同质PN结光电探测器有助于推动其在面阵成像领域中的发展。     

A Compact Ka-Band Planar Three-Way Power Divider

A Ka-band planar three-way power divider which uses the coupled line instead of the transmission line is proposed to reduce chip size. The proposed planar topology, different from the conventional Wilkinson power divider, is analyzed and can provide not only compact but also dc block characteristics, which are very suitable for monolithic microwave integrated circuit applications. The divider implemented by a pHEMT process shows an insertion loss less than 5.1 dB and an output isolation better than 17 dB. A return loss less than 18 dB and a phase difference of 4.2deg at 30 GHz can be achieved. Finally, good agreements between the simulation and experimental results are shown.     

Chip Impedance Evaluation Method for UHF RFID Transponder ICs over Absorbed Input Power

Based on a de‐embedding technique, a new method is proposed which is capable of evaluating chip impedance behavior over absorbed power in flip‐chip bonded UHF radio frequency identification transponder ICs. For the de‐embedding, four compact co‐planar test fixtures, an equivalent circuit for the fixtures, and a parameter extraction procedure for the circuit are developed. The fixtures are designed such that the chip can absorb as much power as possible from a power source without radiating appreciable power. Experimental results show that the proposed modeling method is accurate and produces reliable chip impedance values related with absorbed power.     

A Megapixel Matrix Photodetector of the Middle Infrared Range

Journal of Communications Technology and Electronics - Abstract—The characteristics of MWIRs focal plane aeeays made in the form of a hybrid chip based on a planar n+–p-HgCdTe focal...     

Monolithic integration of a high-performance clustered insulated gate bipolar transistor with low-voltage components to form a 3 kV intelligent power chip

For the first time, we evaluate the feasibility of monolithic integration of low-voltage components, such as n and p channel MOSFETs, into a 3 kV novel planar power semiconductor device, called the clustered insulated gate bipolar transistor, to realise an intelligent power chip. The power device employs MOS control with a thyristor to lower the on-state conduction losses and a unique self-clamping feature that provides current saturation at high gate voltages and enables the incorporation of low-voltage devices without any additional processing. This combination paves the way for realising an intelligent power chip with enhanced performance with respect to on-chip temperature, over-current and over-voltage protection circuitry.     

Ka-Band Monolithic GaAs Balanced Mixers

Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5x0.43 in. This includes the contribution of a 1.5-dB noise figure due to if preamplifier (5-500 MHz).     

Ka-band monolithic GaAs balanced mixers

Monolithic integrated circuits have been developed on semi-insulating GaAs substrates for millimeter-wave balanced mixers. The GaAs chip is used as a suspended stripline in a cross-bar mixer circuit. A double sideband noise figure of 4.5 dB has been achieved with a monolithic GaAs balanced mixer filter chip over a 30- to 32-GHz frequency range. A monolithic GaAs balanced mixer chip has also been optimized and combined with a hybrid MIC IF preamplifier in a planar package with significant improvement in RF bandwidth and reduction in chip size. A double sideband noise figure of less than 6 dB has been achieved over a 31- to 39-GHz frequency range with a GaAs chip size of only 0.5 × 0.43 in. This includes the contribution of a 1.5-dB noise figure due to IF preamplifier (5-500 MHz).     

非梯度折射率型面阵平面微透镜

采用常规的光刻热熔法及灰度掩模技术,结合离子束蚀刻与溅射制作面阵非梯度折射率型平面折射和平面衍射微透镜,定性分析了不同的工艺条件下所得到的平面端面微光学折种和形貌特征。给出了在石英衬底表面通过光刻热熔工艺和氩离子束蚀刻所得到的两种球面及圆弧轮廓特征的面阵册形掩模的表面探针测试曲线,对平面微透镜阵列与IRCCD成像芯片和半导体激光器阵列的集成结构作了初步分析。     

Novel Phase Noise Reduction Method for CPW‐Based Microwave Oscillator Circuit Utilizing a Compact Planar Helical Resonator

This letter describes a compact printed helical resonator and its application to a microwave oscillator circuit implemented in coplanar waveguide (CPW) technology. The high quality (Q)‐factor and spurious‐free characteristic of the resonator contribute to the phase noise reduction and the harmonic suppression of the resulting oscillator circuit, respectively. The designed resonator showed a loaded Q‐factor of 180 in a chip area of only 40% of the corresponding miniaturized hairpin resonator without any spurious resonances. The fully planar oscillator incorporated with this resonator showed an additional phase noise reduction of 10.5 dB at a 1 MHz offset and a second harmonic suppression enhancement of 6 dB when compared to those of a conventional CPW oscillator without the planar helical resonator structure.     

Second-order optical nonlinearity in thermally poled phosphorus-doped silicon dioxide thin-film waveguides

A phosphorus-doped silicon dioxide nonlinear planar waveguide on a GE124 fused silica substrate using plasma-enhanced chemical vapour deposition and thermal poling technique is implemented. The stable second-order nonlinear susceptibility induced in the waveguide is estimated to be around 0.58 pm/V by means of hydrofluoric acid etching, Maker?s fringe measurement and grid search curve fitting using a double-step nonlinear profile. This nonlinear planar waveguide may be applied to fabricate an electrooptic device on the silicon photonic chip.     

基于平面肖特基二极管的平衡式亚毫米波倍频器芯片

基于标准的平面肖特基二极管单片工艺设计了一款平衡式亚毫米波倍频单片集成电路.依据二极管实际结构进行电磁建模,提取了器件寄生参数,并与实测的器件本征参数相结合获得了二极管非线性模型;依据该模型,采用平衡式拓扑结构以实现良好的基波抑制,设计了三线耦合巴伦电桥,并与肖特基二极管集成在同一芯片上,实现了单片集成,提高了设计准确...     

An Integrated Ultra-Wideband Timed Array Receiver in 0.13 μm CMOS Using a Path-Sharing True Time Delay Architecture

A fully integrated CMOS ultra-wideband 4-channel timed array receiver for high-resolution imaging application is presented. A path-sharing true time delay architecture is implemented to reduce the chip area for integrated circuits. The true time delay resolution is 15 ps and the maximum delay is 225 ps. The receiver provides 11 scan angles with almost 9 degrees of spatial resolution for an antenna spacing of 3 cm. The design bandwidth is from 1 to 15 GHz corresponding to less than 1 cm depth resolution in free space. The chip is implemented in 0.13 mum CMOS with eight metal layers, and the chip size is 3.1 mm by 3.2 mm. Measurement results for the standalone CMOS chip as well as the integrated planar antenna array and the CMOS chip are reported.