低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

Design of output buffer with low switching noise and load adaptability

A new CMOS output buffer with low switching noise and load adaptability is presented in this paper. By designing an innovative combination structure of two driving stages, the buffer can reduce switching noise and output ringing with no penalty on signal transmission speed. Furthermore, the buffer can automatically adjust the total driving capability in response to variation of loading condition, the load adaptive method is simple and effective without the necessity for a feedback circuit. The proposed buffer has been designed in a TSMC 90 nm CMOS process. Simulation results demonstrate that the proposed buffer achieves 4.1–53.5% improvements in ground bounce and 2.9–15.2% reductions in output ringing compared with those of the AC/DC buffer. Meanwhile, it reduces ground bounce by 6.5–17.6% and output ringing by 3.8–10.9% relative to the CSR buffer.     

CMOS subnanosecond true-ECL output buffer

An emitter coupled logic (ECL) 100 K compatible output buffer circuit fabricated in a submicrometer CMOS-only process is presented. High speed (0.9-ns delay) and sufficient precision are achieved through the use of a novel circuit principle. Negative feedback and an error correction technique are applied in such a way that external components and/or additional power supplies are not required. Aspects of stability and accuracy are investigated and simulation results are discussed to explain the circuit technique. The actual design and practical aspects of it, such as layout, implementation in silicon, and technology features, are shown. Measured and simulation results, showing the good performance of the ECL output buffer across a wide range of capacitive loading, are presented     

High-speed, low-switching noise CMOS memory data output buffer

This paper describes a data output buffer for highspeed CMOS integrated memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast output transitions by combining output presetting techniques together with adequate driving of the output pull-up and pull-down transistors. Tristate operation and zero static power consumption are also provided. The buffer was integrated in a 16-Mb EPROM device. It occupies 0.06 mm² and ensures a better than 15 ns output transition time with a load capacitor of 100 pF     

用于红外焦平面读出电路的新型输出缓冲器

根据红外焦平面读出电路输出缓冲器的大输出摆幅和大压摆率的特点,设计了一种应用于红外焦平面读出电路的新型输出缓冲器,由于输出缓冲器需要一个较大的输出摆幅,所以采用轨对轨输入以及AB类输出的全差分运放,使其在不损失增益的情况下提高带宽和输出摆幅;并在轨对轨结构中插入恒定跨导电路,使电路更加稳定;在输出缓冲器高压摆率的要求下...     

CMOS data output buffer for integrated memories

A data output buffer for CMOS integrated memories is presented. Output presetting techniques together with a suitable driving of the final transistors are used. The switching noise on supply lines is minimised while high operation speed is preserved. A buffer for a 0.8 mu m EPROM process has been designed using the proposed approach.<>     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color     

A new priority control of ATM output buffer

A new ATM output buffer management strategy with priority control function is proposed, based on four types of cell classes. This strategy can use system resource more effectively, meet the quality of service (QOS) requirements (i.e. cell loss probabilities and delay characteristics) of different services, and also can reduce the complexity of buffer. Furthermore, overload from lower priority traffic doesn't degrade the performance of higher priority traffic (i.e. cell loss rate and cell delay characteristics).     

Low switching noise and load-adaptive output buffer designtechniques

Switching noise due to di/dt is becoming severe as technology states, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per V_DD and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5× and VDD/GND line bounce by 1.7× and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer     

High-speed rail-to-rail output buffer amplifier with dynamic-bias circuit

The design of a high-speed output buffer amplifier for driving the large column line loads of large-size TFT-LCDs is presented. The major circuit of the output buffer is a rail-to-rail current mirror amplifier which can control the class-AB output stage and auxiliary output stage at the same time. The proposed dynamic bias method not only increases the driving capability of the class-AB output stage but also maintains a small quiescent current path.     

一种具有自适应特性的SSO噪声抑制输出驱动电路

介绍了SSO噪声产生的原因,简要概述了常用的抑制SSO噪声的方法.在此基础上,提出了一种具有自适应特点的SSO噪声抑制输出驱动电路,并给出了较详细的分析和比较.     

Service differentiating supporting output circuiting shared optical buffer architecture

A novel buffer architecture for Optical Packet Switching Networks is proposed. The utilization of fiber delay lines and corresponding switch component can be improved obviously; moreover, service differentiating can be achieved effectively. Results and analysis show that the packet delivery ratio is enhanced and the average packet delay is decreased; comparing to the output buffer architecture, the number of optical fiber delay lines of our proposed buffer architecture is reduced, and the complexity is relatively lower.     

Adaptive-biased buffer with low input capacitance

A new analogue buffer, which is a differential-pair-based level shifter followed by an adaptive-biased cascode source follower, is proposed. The structure exhibits low input capacitances, enhanced slew rate, high bandwidth and low distortion. The simulated results have shown input capacitance of 99.5 fF at 1 MHz, slew rate of 55.5 V/μs, -3 dB bandwidth of 37.9 MHz, and THD less than 1% for 1 Vpp input signal up to 6 MHz at a 100 kΩ//15 pF load. The buffer consumes 2.4 mW at 5 V supply in a 0.8 μm n-well CMOS technology     

Integrated NMOS output stage with low output impedance

An NMOS output amplifier stage employing a particular feedback network giving low values of the output impedance is reported. The best results (about 100?) have been obtained with a silicon gate enhancement/depletion technology. Limited values of power and area consumption are required.     

Load-adaptive inter-piconet scheduling in small-scale Bluetooth scatternets

Bluetooth enables wireless communication via ad hoc networks. The basic topology (piconet) is a collection of slaves controlled by a master. A scatternet is a multihop network of piconets. We anticipate that most scatternets will be composed of only a few piconets. However, even in small scatternets, efficient data flow requires the design of inter-piconet scheduling algorithms. Thus, this article presents and evaluates a load adaptive scheduling algorithm tailored for small-scale scatternets. The main advantage of this algorithm is the use of the Bluetooth low-power hold mode, which allows greater flexibility than other low-power modes. A simulation model has been developed in order to evaluate the performance of the algorithm. We show that the results obtained by the model are very close to the analytic results. Then we evaluate the performance of various intra-piconet scheduling algorithms. Finally, we present simulation results regarding inter-piconet scheduling, and compare the proposed algorithm to algorithms using the sniff mode.     

缓冲气体及温度对DPAL输出性能的影响

为进一步提高半导体激光泵浦碱金属蒸汽激光器输出功率,基于三能级速率方程的理论模型,对DPAL的运行进行了模拟,考虑泵浦光带宽,在纵向泵浦的情况下,对缓冲气体气压、增益池长度、温度等参量对激光器输出光强及光光效率的影响进行了计算机模拟,结果表明,一定泵浦光下光光效率随着乙烷气压和温度增加而增大,对一定氦气气压有最大值,模拟结果为实验研究提供了有益的参考。     

40 Gbit/s limiting output buffer in 80 nm CMOS

A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 /spl Omega/ load with a differential output swing of 660 mV and a gain of 18 dB is presented. A power consumption of only 24 mW and a simulated risetime of 11 ps are achieved by means of a systematic buffer optimisation.     

Speedup and buffer division in input/output queuing ATM switches

The capacity of a switch is built out of two factors: space parallelism and speedup. A switch has space parallelism if more than one input port can transmit simultaneously. Speedup is the ratio of the switch's internal link speed over the incoming link speed. An input-queuing switch uses only the first factor (space parallelism), and a share-medium or a share-memory output queuing switch uses only the second factor (speedup). However, to build a large switch, both factors are normally used. A large switch's capacity can be built with less space parallelism (the space factor), but more speedup (the time factor), or vise versa. Buffers are needed at both the input and the output ports. In this paper, we show how to divide the buffers between the input and the output queues and how the optimal division is affected by the (space, time) combinations.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

A 90-nm CMOS 800 MHz 2$$\times$$VDD output buffer with leakage detection and output current self-adjustment

This work presents a 800 MHz 2\(\times\)VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43% after the compensation of the leakage detection. The core area of the prototype is 0.056 \(\times\) 0.439 mm\(^2\), and the power consumption is 68.9/98.5 (\(\upmu\)W/MHz) at 450/800 MHz, respectively.