Pole-residue formulation for transient simulation of high-frequencyinterconnects using householder LS curve-fitting techniques

As digital circuits approach the GHz range, and as the need for high performance wireless devices increases, new simulation tools which accurately characterize high frequency interconnects are needed. In this paper, a new macromodeling algorithm for time domain simulation of interconnects is presented. The algorithm incorporates Householder LS curve-fitting techniques. The approach generates a universal macromodeling tool that enables simulation of interconnects in a modified version of simulation program with integrated circuit emphasis (SPICE). This results in a method that conveniently incorporates accurate EM models of interconnects or experimental data into a circuit simulator. The time domain simulation results using this new tool are compared with results from other simulators     

A comprehensive two-dimensional VLSI process simulation program, BICEPS

Bell Integrated Circuit Engineering Process Simulator (BICEPS) is a comprehensive VLSI process-simulation program developed at Bell Laboratories. BICEPS incorporates the most up-to-date physical models and efficient numerical algorithms to make it a highly robust and general-purpose program. BICEPS can calculate doping profiles resulting from ion implantation, predeposition, oxidation, and epitaxy in one or two spatial dimensions as well as etching and deposition of oxide, nitride, and photoresist. In this paper, the physics of IC process simulation will be reviewed with an emphasis on the various physical models implemented in BICEPS. Calculation of the impurity profiles in VLSI devices involves the solution of a coupled set of nonlinear time-dependent partial differential equations, with moving boundaries and in more than one spatial dimension. The numerical techniques in obtaining a solution to this problem, namely, spatial discretization, time discretization, and the treatment of moving boundaries are also described in this paper. The capabilities of BICEPS are illustrated by the results of simulation of the fabrication of a typical NMOS transistor.     

An automatic concurrent error detecting tool for PLA generation

Programmable Logic Arrays (PLA) are often used in the design of VLSI circuits, because of their regular structure and flexibility. It has been reported that the major source of errors in the operation of such devices is the occurrence of soft or transient faults. Such faults can only be detected by on-line testing techniques, known as Concurrent Error Detection (CED). Most CAD tools provide a generator for automatically producing a PLA. In order to incorporate CED it is necessary to significantly modify the function. This process would be very time consuming and tedious for a designer not acquainted with all the CED techniques available. In this paper we describe a tool for the design of PLAs which incorporates CED.     

Technology transfer between VLSI design and software engineering: CAD tools and design methodologies

Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of applications of these technologies to software engineering. Then, three research projects are described which focused on applying software engineering principles to the VLSI design process. They are: a methodology, language, and assessment tool for multilevel mixed-mode VLSI designs; a research project that explored the potential for transfer of software design methodologies for managing VLSI design complexity; and a specification technique for "modules" in a VLSI design that localizes the impact of changes to the design. Next, a CAD tool and design methodology are described which consider the design of software and hardware together, and apply common techniques to both. Finally, some observations are made on the appropriateness of technology transfer between VLSI design and software engineering.     

Simulation of three-dimensional effects in VLSI devices

Two dimensional (2D) modelling of electron devices is already established as an indispensable tool for VLSI design, and a number of very sophisticated 2D device simulators have been developed. The increasing miniaturization and packing density of VLSI circuits is now boosting research activity towards three-dimensional (3D) device simulation. In this paper we present some results obtained with our prototype 3D simulator. HFIELDS-3D, and discuss some topics related to the underlying philosophy and to the implementation of a vector code, which we are now exploiting on a CRAY XMP48 machine.     

A technique for modelling p-n junction depletion capacitance of multiple doping regions in integrated circuits

The continuing advancements in integrated circuit technology have placed new burdons on the circuit design engineer, who must rely extensively upon computer simulation to correctly predict circuit behavior. One challenge is to develop better modelling techniques to more accurately deal with complex p-n junction structures often used in modern VLSI designs. This paper presents an easily implemented method for deriving parameters which accurately model the behavior of MOS VLSI structures containing complex p-n junction capacitance components. The methodology is applicable to both planar and laterally diffused junctions, whether formed by direct ion implantation or by diffusion from a finite or infinite source. The theories behind the equations used and results of the application of this new technique are discussed. A flow chart for a fitter program based on the new method is presented and described. The corresponding program written for the TI-59 scientific programmable calculator is available. Final model parameters are given and are shown to produce a numerical capacitance model which is accurate to within 2%.     

RECIPE—A two-dimensional VLSI process modeling program

REnsselaer Computer integrated Circuits Process Engineering (RECIPE) is a two-dimensional (2-D) integrated circuit process modeling program developed for use in VLSI applications. The program incorporates a 2-D diffusion model which includes the concentration dependence of the diffusion coefficients. An incremental solution method is used to compute the appropriate diffusion coefficients as a function of impurity concentration throughout space. RECIPE also incorporates a 2-D ion-implantation model. While intended as a general-purpose modeling program, RECIPE has been used to study channel-length decrease of short-channel MOSFET's during high-temperature processing. A typical phosphorus-implanted (150 keV, 10¹⁶/cm²) 1-µm gate transistor had no channel after processing for 60 min at 1000°C, while an arsenic-implanted device had an effective channel length of ∼ 0.1 µm after similar processing.     

A recursive design methodology for VLSI: Theory and example

A novel VLSI (Very Large Scale Integration) methodology based on the hierarchical design of computational and system blocks is presented. The underlying algorithms used are shown to optimise the area-time complexity (AT²) of the computational units and at the system design level. The technique is illustrated for a matrix-matrix multiplication by using an image processing window convolver. This paper describes the performance of the recursive design technique comparing it to a typical systolic array, and demonstrates how data word size and convolution size may be expanded by movement up the architectural hierarchy. A prototype CAD (Computer Aided Design) autolayout program is described which maps directly into the hierarchical design environment. Using such design aids, flexible and correct designs may be generated which offer very simple data flow and highly local interconnection, with high performance.     

Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs

Today's microelectronics researchers design VLSI devices to achieve highly differentiated devices, both in performance and functionality. As VLSI devices become more complex, VLSI device testing becomes more costly and time consuming. The increasing test complexity leads to longer device test programs development time as well as more expensive test systems, and debugging test programs is a great burden to the test programs development. On the other hand, there is little formal theory of debugging, and attempts to develop a methodology of debugging are rare. The aim of the investigation in this paper is to create a theory to support analysis and debugging of VLSI device test programs, and then, on the basis of this theory, design and develop an off-line debugging environment, OLDEVDTP, for the creation, analysis, checking, identifying, error location, and correction of the device test programs off-line from the target VLSI test system, to achieve a dramatic cost and time reduction. In the paper, fuzzy comprehensive evaluation techniques are applied to the program analysis and debugging process to reduce restrictions caused by computational complexity. Analysis, design, and implementation of OLDEVDTP are also addressed in the paper.     

Optoelectronic integrated systems based on free-space interconnectswith an arbitrary degree of space variance

It is appealing to contemplate how VLSI or wafer-scale integrated systems incorporating free-space optical interconnection might outperform purely electrically interconnected systems. This paper first provides a uniform treatment of a general class of optical interconnects based on a Fourier-plane imaging system with an array of sources in the object plane and an array of receptors in the image plane. Sources correspond to data outputs of processing “cells,” and receptors to their data inputs. A general abstract optical imaging model, capable of representing a large class of real systems, is analyzed to yield constructive upper bounds on system volume that are comparable to those arising from “3-D VLSI” computational models. These bounds, coupled with technologically derived constraints, form the heart of a design methodology for optoelectronic systems that uses electronic and optical elements each to their greatest advantage, and exploits the available spatial volume and power in the most efficient way. Many of these concepts are embodied in a demonstration project that seeks to implement a bit-serial, multiprocessing system with a radix-2 butterfly topology, and incorporates various new technology developments     

Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems

New challenges have been brought to fault-tolerant computing and processor architecture research because of developments in IC technology. One emerging area is development of architectures, built by interconnecting a large number of processing elements on a single chip or wafer. Two important areas, related to such VLSI processor arrays, are the focus of this paper; they are fault-tolerance and yield improvement techniques. Fault tolerance in these VLSI processor arrays is of real practical significance; it provides for much-needed reliability improvement. Therefore, we first describe the underlying concepts of fault tolerance at work in these multiprocessor systems. These precepts are useful to then present certain techniques that will incorporate fault tolerance integrally into the design. In the second part of the paper we discuss models that evaluate how yield enhancement and reliability improvement may be achieved by certain fault-tolerant techniques.     

A mixed-mode sampled-data simulation program

A program which allows the simulation of mixed sampled data, continuous analog and digital signal processing systems is presented. The intention is to support the VLSI implementation of communication applications. Particular focus is on switched-capacitor filters, digital delay-line structures, A/D converters, and arbitrary analog and digital functional models. The program's efficiency allows it to be used as a tool to explore signal processing algorithms in a form tied to the proposed VLSI realization.     

A methodology aimed at better integration of functional verification and RTL design

The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.     

A new quantum effect model for practical device simulation

An increase in the complexity of VLSI design, especially in process integration, is leading to increased demands for technology CAD (TCAD). The quantum mechanical (QM) effect becomes very important with an increase in the channel impurity concentration. Several models for the QM effect have been proposed. However, it has been reported that these models had some problems. In this paper, a new QM model for a conventional device simulator is proposed. Applications of this model to NMOS and PMOS including the buried-channel are examined     

Electro-thermal and logi-thermal simulation of VLSI designs

Due to severe thermal problems of today's VLSI integrated circuits the need for reliable and quick thermal, electro-thermal and logi-thermal simulation tools is increasing, In this paper, we discuss the latest advances in the SISSI package (simulator for integrated structures by simultaneous iteration) which is a tool developed originally for analog VLSI design. The improvements include electro-thermal ac and transient simulation and the consideration of the thermal voltage of Si-Al contacts. Furthermore, we introduce a new module of SISSI, LOGITHERM, which is aimed at the self-consistent logic and thermal simulation of large digital VLSI designs. The features of our simulator package are highlighted by simulation examples that are compared in most cases with measurement results     

Common-mode failures in redundant VLSI systems: a survey

This paper presents a survey of CMF (common-mode failures) in redundant systems with emphasis on VLSI (very large scale integration) systems. The paper discusses CMF in redundant systems, their possible causes, and techniques to analyze reliability of redundant systems in the presence of CMF. Current practice and results on the use of design diversity techniques for CMF are reviewed. By revisiting the CMF problem in the context of VLSI systems, this paper augments earlier surveys on CMF in nuclear and power-supply systems. The need for quantifiable metrics and effective models for CMF in VLSI systems is re-emphasized. These metrics and models are extremely useful in designing reliable systems. For example, using these metrics and models, system designers and synthesis tools can incorporate diversity in redundant systems to maximize protection against CMF     

Tools for the computer-aided design of multigigahertzsuperconducting digital circuits

The realization of large integrated circuits depends upon the application of computer-aided design (CAD) tools. This paper summarizes the results of a survey of CAD tools targeting superconducting digital electronics. Five categories of tools: circuit simulators, circuit optimizers, layout tools, inductance estimators, and logic simulators are discussed in detail. Within each category, a comparison of several currently available CAD tools is presented, and a tool which has been adapted for use or developed at the University of Rochester is discussed in greater detail. In addition, tools for timing analysis as well as integrated design environments that permit the effective data interchange among various tools and support libraries of design models are discussed. Future tools for timing optimization, automated logic synthesis, and automated layout synthesis are shown to be necessary for the design of superconducting circuits at the very large scale of integration (VLSI) level of integration. Trends regarding changes in the requirements for effective CAD tools are discussed, and expected improvements to existing tools and features of new tools currently under development are presented     

Defect tolerance in VLSI circuits: techniques and yield analysis

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit “defect tolerant”, i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits