WCDMA功放预失真发生器的研究

针对宽带码分多址(WCDMA)功放的非线性失真问题,提出了一种简单有效的解决方案,即通过预失真发生器对幅度-幅度(AM-AM)及幅度-相位(AM-PM)曲线进行调整,以补偿功放的非线性失真.这种方案主要是通过利用二极管的非线性特性设计出的预失真发生器来实现的.实验证明,将预失真发生器与WCDMA功放配合使用,能将功放的邻道功率泄漏比(ACPR)改善5 dB.     

一种高效的用于RF功率放大器线性化的自适应预失真结构

分析了当前文献中主要的几种自适应预失真结构,发现这些自适应预失真结构均不利于高效最小二乘算法的直接应用,从而限制了预失真技术的自适应性能.提出了一种新的自适应预失真结构,可直接使用高效的最小二乘算法对预失真器进行自适应更新.仿真结果表明利用此结构可快速、高效地实现非线性RF功率放大器的线性化.     

WCDMA multicarrier receiver for base-station applications

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-/spl mu/m SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply.     

Ka频段10 W自适应射频预失真线性化固态功放研制

射频功率放大器的特性会随信道切换、环境温度、工作状态等多种因素发生变化,为了保证功率放大器的优良工作特性,具有自适应性能的预失真系统就显得非常重要。提出了一种自适应反馈检测方法,以减小放大器输出信号的幅度失真和相位失真作为系统自适应的优化目标,采用多方向搜索优化算法对预失真系统进行优化调整,使系统始终处于最优工作状态。研制了工作于Ka频段10 W自适应射频预失真线性化固态功放原理样机,当工作温度为-40℃~+60℃时,在3 GHz的工作带宽内,三阶交调指标优于-32 dBc。测试结果表明该功放具有工作频带宽、温度适应性广等特点。     

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.     

A high average-efficiency SiGe HBT power amplifier for WCDMA handset applications

The linearity of a silicon-germanium (SiGe) HBT power amplifier (PA) is analyzed with the help of a power-dependent coefficient Volterra technique. The effect of emitter inductance is included and the dominant sources of nonlinearity are identified. A dynamic current biasing technique is developed to improve the average power efficiency for wide-band code-division multiple-access (WCDMA) PAs. The average power efficiency is improved by more than a factor of two compared to a typical class-AB operation, while the power gain keeps roughly constant. The measured adjacent channel power ratio with 5and 10-MHz offsets at 23.9-dBm average channel output power are -33 and -58.8 dBc, respectively, and satisfies the Third-generation partnership project WCDMA specifications. The output power at the 1-dB compression point is 25.9 dBm     

An adaptive digital predistortion for compensating nonlinear distortions in RF power amplifier with memory effects

In this paper, an adaptive digital predistortion based on a memory polynomial model is proposed in order to linearize the power amplifier with memory effect. The coefficients of the power amplifier model have been extracted using a least square method and those of predistortion have been identified by applying an indirect learning structure. Finally, the performance of digital predistortion has been demonstrated using the simulation of the power amplifier and the digital predistortion excited by a modulated 16 QAM signal in Matlab software. According to the simulation results, the criterion of adjacent channel power ratio (ACPR) declined by around 15 dB and the input/output power spectrum density of the power amplifier has quite similar curves. The linearized power amplifier output spectrum demonstrates the superiority of the proposed predistorter in eliminating the spectral regrowth which is caused by the memory effect in comparison to the other linearization methods.     

Parasitic-aware design and optimization of a CMOS RF power amplifier

Implementation of fully integrated CMOS RF power amplifiers is a challenge owing to the low breakdown voltage of aggressively scaled CMOS transistors and parasitic effects associated with on-chip passive components. To address this problem, a parasitic-aware design and optimization paradigm and novel power amplifier circuit design techniques are proposed. The parasitic-aware synthesis described herein employs a simulated annealing algorithm that includes an adaptive tunneling mechanism and post-optimization sensitivity analysis (i.e., design centering) with respect to process, voltage, and temperature variations. Several design techniques are introduced including a self-biased power-amplifier configuration and a digitally controlled conduction angle topology. The techniques are validated via the design of a fully differential nonlinear three-stage 900-MHz GSM power amplifier integrated in 2 mm/sup 2/ in 250-nm CMOS that outputs 2 W (1.5 W) with 30% (43%) drain efficiency from a single 3.0-V (2.5-V) power supply.     

Wiener功率放大器的一种简化预失真方法

根据Hammerstein模型的一种最优两步辨识算法的思路,针对预失真技术的特点对Hammerstein模型进行了两次转换,建立了一种等效的但形式简单的记忆非线性预失真器模型——非线性抽头延时多项式模型,从而简化了Wiener功放的预失真。仿真结果表明,利用所提出的记忆预失真器模型能使用较少的参数,快速、简便地实现记忆放大器的预失真,而且具有满意的线性化性能。     

Chip for wideband digital predistortion RF power amplifierlinearisation

The authors present a custom chip for use in digital predistortion linearisation of RF power amplifiers. The chip is mainly implemented with systolic arrays. At maximum clock-rate, 130 MHz, the throughput is 16 Msamples/s with a 5 V supply voltage and power consumption of 1 W. A throughput of 2 Msamples/s is achieved at a 1.2 V supply voltage with 6 mW power consumption     

Complexity-reduced Volterra series model for power amplifier digital predistortion

This paper expounds a complexity-reduced Volterra series model for radio frequency power amplifier (PA) behavioral modeling and digital predistortion (DPD). An analysis was conducted, which took into account the memory effect mechanisms of the PA. This led to a closed-form expression that relates the memoryless behavior of the PA to the finite impulse response feedback filter, which approximates the memory effects’ behavior. The analysis resulted in a complexity-reduced Volterra series model which allows for a substantial reduction in the requirements for digital signal processors and the time needed to construct and implement the DPD in a real-time environment. The proposed model was validated as a behavioral model and a DPD using two different PA architectures, employing two different transistor technologies, driven by both 20 MHz 1001 wideband code division multiple access and long term evolution signals. The results obtained demonstrate the excellent modeling and linearization capability of the complexity-reduced Volterra series model.     

Dynamically optimum lookup-table spacing for power amplifier predistortion linearization

The lookup-table-based digital adaptive predistortion (DAPD-LUT) approaches are low cost and effective for power amplifier (PA) linearization in wireless applications. However, most existing DAPD-LUT schemes are sub-optimum because they adopt uniformly spaced LUTs regardless of the system state information (SSI), i.e., the PA characteristics and the input signal statistics. Other existing DAPD-LUT schemes assume either full or partial knowledge of the SSI to optimize and then to freeze the LUT spacing. Without prior knowledge of the SSI, we propose an SSI-learning low-complexity procedure to optimize the LUT spacing for a DAPD-LUT scheme. The proposed procedure is capable of online adapting the LUT spacing for PAs with various nonlinear characteristics, for input signals with various statistics, and for wireless environments with various time-varying properties.     

Performance-reliability trade-offs in short range RF power amplifier design

In this work, trade-offs between performance and reliability in CMOS RF power amplifiers at the design stage are studied. The impact of transistor sizing, amplifier class and on-chip matching network design are explored for a 130 nm technology and the implications of design decisions in transistor gate oxide reliability are discussed and projected. A strong trade-off is observed between efficiency and reliability, mainly for different on-chip output matching architectures. A comparison between two example designs is performed via SPICE simulations that include reliability models and the effects of aging on the stress conditions of each amplifier.     

Neural-network-based adaptive baseband predistortion method for RF power amplifiers

An adaptive baseband predistortion method for RF power amplifier (PA) linearization is proposed and experimentally demonstrated. The predistortion component is implemented by a single-input dual-output multilayer perceptron (MLP). Both amplitude-to-amplitude and amplitude-to-phase distortion products are compensated by backpropagation training of the neural network including the response of the PA. Effects of modulator and demodulator imperfections on system performance are examined. Measurements on a system prototype reveal a significant linearity improvement that reaches 25 dB.     

CDMA射频线性功率放大器

该文对前馈线性校正射频功率放大器进行了分析,给出了分析结果。并用该结果指导设计了CDMAIS-95基站射频线性功率放大器,放大器增益47dB,连续波输出功率60W,在通频带内三阶交调改善了23dB。     

A new diode-based curve-fitting predistortion lineariser for GaN power amplifier

In this article, a new strategy is presented for selecting the breakpoints on a typical characteristic of a lineariser for a saturating nonlinear amplifier. As a proof of concept, using this strategy, a new Schottky-diode based curve-fitting predistortion lineariser for a 1.65?GHz centre frequency, 50?MHz bandwidth, 30?W GaN power amplifier is developed. The proposed lineariser is tested using the two-tone test and the Quadrature Phase-Shift Keying (QPSK) modulated signal. The results show that a 3?dB improvement in the overall gain of the linearised amplifier is achieved. Moreover, for output power levels up to 36?dBm, the linearised power amplifier provides better rejection of the third-order intermodulation. Because of the hard nonlinearity of the GaN power amplifier at the high end, this improvement in intermodulation rejection vanishes for output power levels around 41?dBm.     

改进的动态记忆多项式功放模型及预失真应用

针对无线通信系统中射频功放的强非线性、强记忆效应特征,提出一种改进的多支路组合模型——改进的动态记忆多项式(G-DMP)模型。该模型以动态记忆多项式模型为基础,引入记忆时刻输入信号包络对当前输入信号的影响项和当前输入信号包络对记忆时刻输入信号的影响项,更灵活地对功放强记忆效应建模。同时采用改进的RLS_LMS联合算法对G-DMP模型进行自适应预失真系统仿真。结果表明:G-DMP模型比DMP模型精度优于0.5dB时,系数减少14.29%,邻信道功率比(ACPR)改善了4dB,由此可知,G-DMP模型能获得更好的建模精度和线性化效果。     

A dual-band RF front-end for WCDMA and GSM applications

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-μm BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively     

Junction-gate FET RF power amplifier

A junction-gate power field-effect transistor of recent design has been found to yield greater than 25 watts CW at 30 MHz in two modes of circuit configuration. In this investigation, favorable characteristics are explored for potential device utility as a high-reliability low-distortion RF power amplifier.     

射频功率放大器的建模

提出了运用模糊神经网络对射频功放电路进行建模的方法,模糊神经网络是近年来发展起来的一种新型的网络结构,具有万能函数逼近器的功能,文中用MATALAB中自带的自适应神经模糊系统ANFIS对仿真得到的数据进行建模,并利用得到的模型计算功放的频谱,功率压缩曲线,功率增益曲线,与ADS仿真的结果进行比较,取得了较好的结果,证明了建模方法的有效性.