WCDMA multicarrier receiver for base-station applications

The multicarrier receiver IC described in this paper receives four adjacent WCDMA channels simultaneously in order to reduce the component count of a base-station. The receiver uses low-IF architecture and it is fabricated with a 0.25-/spl mu/m SiGe BiCMOS process to meet the high-performance requirements set by the base-station application. The receiver includes a dual-input low-noise amplifier (LNA), quadrature mixers, a local-oscillator (LO) divider, IIP2 calibration circuits, 10-MHz low-pass filters, and ADC buffers. The receiver noise figures, measured over the downconverted WCDMA channels centered at 2.5-MHz and 7.5-MHz intermediate frequencies, are 3.0 dB and 2.6 dB, respectively. The receiver achieves 47-dB voltage gain and -12-dBm out-of-band IIP3 and consumes 535mW from a 2.5-V supply.     

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.     

A high average-efficiency SiGe HBT power amplifier for WCDMA handset applications

The linearity of a silicon-germanium (SiGe) HBT power amplifier (PA) is analyzed with the help of a power-dependent coefficient Volterra technique. The effect of emitter inductance is included and the dominant sources of nonlinearity are identified. A dynamic current biasing technique is developed to improve the average power efficiency for wide-band code-division multiple-access (WCDMA) PAs. The average power efficiency is improved by more than a factor of two compared to a typical class-AB operation, while the power gain keeps roughly constant. The measured adjacent channel power ratio with 5and 10-MHz offsets at 23.9-dBm average channel output power are -33 and -58.8 dBc, respectively, and satisfies the Third-generation partnership project WCDMA specifications. The output power at the 1-dB compression point is 25.9 dBm     

Parasitic-aware design and optimization of a CMOS RF power amplifier

Implementation of fully integrated CMOS RF power amplifiers is a challenge owing to the low breakdown voltage of aggressively scaled CMOS transistors and parasitic effects associated with on-chip passive components. To address this problem, a parasitic-aware design and optimization paradigm and novel power amplifier circuit design techniques are proposed. The parasitic-aware synthesis described herein employs a simulated annealing algorithm that includes an adaptive tunneling mechanism and post-optimization sensitivity analysis (i.e., design centering) with respect to process, voltage, and temperature variations. Several design techniques are introduced including a self-biased power-amplifier configuration and a digitally controlled conduction angle topology. The techniques are validated via the design of a fully differential nonlinear three-stage 900-MHz GSM power amplifier integrated in 2 mm/sup 2/ in 250-nm CMOS that outputs 2 W (1.5 W) with 30% (43%) drain efficiency from a single 3.0-V (2.5-V) power supply.     

Chip for wideband digital predistortion RF power amplifierlinearisation

The authors present a custom chip for use in digital predistortion linearisation of RF power amplifiers. The chip is mainly implemented with systolic arrays. At maximum clock-rate, 130 MHz, the throughput is 16 Msamples/s with a 5 V supply voltage and power consumption of 1 W. A throughput of 2 Msamples/s is achieved at a 1.2 V supply voltage with 6 mW power consumption     

Complexity-reduced Volterra series model for power amplifier digital predistortion

This paper expounds a complexity-reduced Volterra series model for radio frequency power amplifier (PA) behavioral modeling and digital predistortion (DPD). An analysis was conducted, which took into account the memory effect mechanisms of the PA. This led to a closed-form expression that relates the memoryless behavior of the PA to the finite impulse response feedback filter, which approximates the memory effects’ behavior. The analysis resulted in a complexity-reduced Volterra series model which allows for a substantial reduction in the requirements for digital signal processors and the time needed to construct and implement the DPD in a real-time environment. The proposed model was validated as a behavioral model and a DPD using two different PA architectures, employing two different transistor technologies, driven by both 20 MHz 1001 wideband code division multiple access and long term evolution signals. The results obtained demonstrate the excellent modeling and linearization capability of the complexity-reduced Volterra series model.     

Dynamically optimum lookup-table spacing for power amplifier predistortion linearization

The lookup-table-based digital adaptive predistortion (DAPD-LUT) approaches are low cost and effective for power amplifier (PA) linearization in wireless applications. However, most existing DAPD-LUT schemes are sub-optimum because they adopt uniformly spaced LUTs regardless of the system state information (SSI), i.e., the PA characteristics and the input signal statistics. Other existing DAPD-LUT schemes assume either full or partial knowledge of the SSI to optimize and then to freeze the LUT spacing. Without prior knowledge of the SSI, we propose an SSI-learning low-complexity procedure to optimize the LUT spacing for a DAPD-LUT scheme. The proposed procedure is capable of online adapting the LUT spacing for PAs with various nonlinear characteristics, for input signals with various statistics, and for wireless environments with various time-varying properties.     

Neural-network-based adaptive baseband predistortion method for RF power amplifiers

An adaptive baseband predistortion method for RF power amplifier (PA) linearization is proposed and experimentally demonstrated. The predistortion component is implemented by a single-input dual-output multilayer perceptron (MLP). Both amplitude-to-amplitude and amplitude-to-phase distortion products are compensated by backpropagation training of the neural network including the response of the PA. Effects of modulator and demodulator imperfections on system performance are examined. Measurements on a system prototype reveal a significant linearity improvement that reaches 25 dB.     

A new diode-based curve-fitting predistortion lineariser for GaN power amplifier

In this article, a new strategy is presented for selecting the breakpoints on a typical characteristic of a lineariser for a saturating nonlinear amplifier. As a proof of concept, using this strategy, a new Schottky-diode based curve-fitting predistortion lineariser for a 1.65?GHz centre frequency, 50?MHz bandwidth, 30?W GaN power amplifier is developed. The proposed lineariser is tested using the two-tone test and the Quadrature Phase-Shift Keying (QPSK) modulated signal. The results show that a 3?dB improvement in the overall gain of the linearised amplifier is achieved. Moreover, for output power levels up to 36?dBm, the linearised power amplifier provides better rejection of the third-order intermodulation. Because of the hard nonlinearity of the GaN power amplifier at the high end, this improvement in intermodulation rejection vanishes for output power levels around 41?dBm.     

改进的动态记忆多项式功放模型及预失真应用

针对无线通信系统中射频功放的强非线性、强记忆效应特征,提出一种改进的多支路组合模型——改进的动态记忆多项式(G-DMP)模型。该模型以动态记忆多项式模型为基础,引入记忆时刻输入信号包络对当前输入信号的影响项和当前输入信号包络对记忆时刻输入信号的影响项,更灵活地对功放强记忆效应建模。同时采用改进的RLS_LMS联合算法对G-DMP模型进行自适应预失真系统仿真。结果表明:G-DMP模型比DMP模型精度优于0.5dB时,系数减少14.29%,邻信道功率比(ACPR)改善了4dB,由此可知,G-DMP模型能获得更好的建模精度和线性化效果。     

Junction-gate FET RF power amplifier

A junction-gate power field-effect transistor of recent design has been found to yield greater than 25 watts CW at 30 MHz in two modes of circuit configuration. In this investigation, favorable characteristics are explored for potential device utility as a high-reliability low-distortion RF power amplifier.     

A dual-band RF front-end for WCDMA and GSM applications

An RF front-end for dual-band dual-mode operation is presented. The front-end consumes 22.5 mW from a 1.8-V supply and is designed to be used in a direct-conversion WCDMA and GSM receiver. The front-end has been fabricated in a 0.35-μm BiCMOS process and, in both modes, can use the same devices in the signal path except the LNA input transistors. The front-end has a 27-dB gain control range, which is divided between the LNA and quadrature mixers. The measured double-sideband noise figure and voltage gain are 2.3 dB, 39.5 dB, for the GSM and 4.3 dB, 33 dB for the WCDMA, respectively. The linearity parameters IIP3 and IIP2 are -19 dBm, +35 dBm for the GSM and -14.5 dBm and +34 dBm for the WCDMA, respectively     

A hybrid digital/RF envelope predistortion linearization system for power amplifiers

This paper presents an adaptive wide-band digitally controlled RF envelope predistortion linearization system for power amplifiers (PAs). A field-programmable gate-array-based lookup table is indexed by a digitized envelope power signal, and instantaneously adjusts the input signal amplitude and phase via an RF vector modulator to compensate for the AM-AM and AM-PM distortion. The advantages of this predistortion architecture over conventional baseband digital approaches are that a 20%-33% wider correction bandwidth is achievable at the same clock speeds, and linearization can be performed without the need for a digital baseband input signal. The timing match between the input RF signal and predistorting signal, which is one of the critical factors for performance, was investigated and adjusted to obtain optimum performance. Using three-carrier cdmaOne and wide-band multitone signals, the linearization performances for a 0.5-W GaAs heterostructure field-effect transistor, a 90-W peak-envelope-power (PEP) silicon LDMOS PA, and a 680-W PEP LDMOS PA were examined. In addition, the predistortion performance variation for different signals was studied in terms of signal envelope statistics, output powers, and PA power capacities.     

高效率E类射频功率放大器

研究了E类RF放大器的电路结构、工作原理、存在问题以及解决的方法--差分和交叉耦合反馈结构,最后给出了E类放大器的实例.由于具有低成本、高集成度、多功用等优点,MOS工艺在射频功率放大方面有很大的发展潜力.在本文中,用0.6 u m CMOS工艺实现了E类放大器的设计.     

移动终端射频功放的动态电源管理与控制

本文研究WCDMA移动终端射频功放供电效率问题.分析了射频功放特性和电池放电特性,给出了考虑射频输出功率分布的动态电源管理方案和控制算法,分析结果表明:与常规的电池直接供电方案相比较,按照移动终端在城市的发射功率分布模型,新方案射频功放所需的平均功率降低了3.5倍,可以大大延长手机通话和待机时间.     

Envelope-domain time series (ET) behavioral model of a Doherty RF power amplifier for system design

In this paper, we present an envelope-domain behavioral model of a high-power RF amplifier. In this modeling approach, we use the signal envelope information, and the behavioral model is generated using an established nonlinear time-series approach to create a time-domain model that operates in the envelope or signal domain. We have generated a model of a 200-W Doherty amplifier from measured IQ data taken using a wideband code-division multiple-access excitation; the amplifier was driven from the linear regime into saturation. The time-series model was created using a time-delay embedding identified from auto-mutual information analysis, and an artificial neural network was used to fit the multivariate transfer function. The model has been validated using measured and simulated data, and it has been used in the development of a system-level design of a digital pre-distorter.     

Design of N-way distributed Doherty amplifier for WCDMA and OFDM applications

A novel three-way distributed Doherty power amplifier with an extended efficiency range for WCDMA or OFDM repeater or base-station applications is presented. This distributed Doherty amplifier consists of one main amplifier and two peaking amplifiers. To achieve high efficiency at a high back-off power, the peaking amplifier structure is based on the dual-fed distributed amplifier form. The 2140 MHz measured results of the three-way distributed Doherty amplifier yielded an 11 dB power gain, with 39.5% power added efficiency at 9.5 dB back-off power     

One GHz class E RF power amplifier for a polar transmitter

This paper describes advantages and characteristics of a class E power amplifier when used in a polar transmitter system. Basic principles of class E operation and information about different nonlinearities are given. Also, modifying the transistor model for switch-mode use is discussed briefly. A 1 GHz, 0.5 W class E power amplifier was implemented for a polar transmitter. Performance measurements of a total transmitter system with and without predistortion are presented.     

基于BP神经网络的功放自适应预失真

提出用神经网络的方法来实现功放的自适应预失真模型。它利用BP神经网络的函数逼近能力，来学习功放预失真器的MM/AM、AM/PM特性函数，以抵消由于功放非线性引起的信号失真和交扰；同时，也通过自适应地调整幅度和相位两个神经网络的权、阈值，来跟踪放大器的特性变化。仿真结果证实了基于神经网络的预失真模型的有效性和低复杂性。