High-performance coherent demodulator LSIC for wireless personalcommunications

This paper presents a high-performance coherent π/4-shift differential quaternary phase shift keying (DQPSK) demodulator (large scale integrated circuit) LSIC for the personal communication system in Japan, which is implemented on a 2-V operation 0.8-μm CMOS standard cell. The developed LSIC achieves a better bit error rate (BER) and frame error rate (FER) performance and a lower power consumption than conventional demodulators by employing new schemes: (1) a reverse-modulation carrier recovery circuit with a -π/4 phase rotator and a bandwidth-changeable carrier filter; (2) a bit timing recovery circuit using an initial bit timing estimation scheme; and (3) a fully digital orthogonal detector suitable for low power consumption. Performance evaluation confirms that the developed demodulator LSIC reduces the irreducible frame error rate by 40% and achieves an Eb/No improvement of 3 dB at an FER of 10^-1 compared with differential detection in the Rayleigh fading typical of personal communication channels     

A -80 dB THD, 4 Vpp switched capacitor filter for 1.5 Vbattery-operated systems

A fully differential fifth-order SC filter that can operate from power supplies as low as 1.5 V featuring a -80 dB THD up to 4 V_pp output voltage is presented. A measured p-weighted noise of 120 μV_rms leads to a dynamic range of 81.5 dB. This circuit is used as reconstruction filter for a low voltage 14-b DAC. The very low voltage operation has been possible by integrating a regulated voltage-multiplier on the same chip. The filter active area is 0.54 mm ² in a 0.8 μm CMOS technology. Typical power consumption is 0.8 mW at 1.5 V supply     

Low-power and high-quality signal transmission baseband LSIC forpersonal communications

This paper presents a very low power consumption one-chip baseband large-scale integrated circuit (LSIC) for personal communication terminals. It comprises a π/4-shift QPSK modem, an adaptive differential pulse code modulation (ADPCM) codec, a time division multiple access time division duplex (TDMA-TDD) controller and a link access procedure for a digital cordless (LAPDC: Layer-2 protocol) controller. The developed LSIC meets all the specifications of the personal handy-phone system (PHS) standard. By employing a novel coherent demodulator and an ADPCM codec with a click noise suppressor, a higher quality voice transmission has been achieved in a fading environment. In addition, it has 61-kb/s data transmission capability to achieve wireless multimedia services based on PHS. Moreover, the novel circuit configurations of the modem, the ADPCM codec, the TDMA-TDD controller, and the LAPDC controller achieve significant power reduction of the baseband circuits (57.4 mW) of personal communication terminals. It enables very low power consumption wireless multimedia terminals to be achieved based on the PHS common air interface     

一种新型电容修调RC振荡器

为了降低RC振荡器的功耗,并提高振荡频率的稳定性,提出一种新型的RC振荡器电路。该振荡器采用单比较器,结合电容修调结构。基于0.35 μm BCD工艺及Hspice 仿真工具,完成了电路的设计和仿真,仿真结果表明,该振荡器正常工作频率为51 kHz,由于温度和电源电压变异,频率变化范围为47.54~53.97 kHz,最大功耗电流为2.1 μA,面积为150 μm×180 μm,具有较低的功耗,可以提供相对稳定的频率,能够应用于电源管理芯片。     

Weak inversion four-quadrant multiplier and two-quadrant divider

A four-quadrant multiplier and a two-quadrant divider are presented. The proposed circuits are implemented by MOSFETs operating in weak inversion and are therefore suitable for low voltage and low power applications. Their performances were confirmed by HSPICE simulation using a 0.8 μm CMOS process. The multiplier can operate under a ±0.75 V supply voltage and its linear input range is ~0.125 μA with error <2%. The input range of the divider is 0.5-2 μA and the error is <3% for divider current <60 nA     

Compact low voltage four quadrant CMOS current multiplier

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz     

Application of merged current switch logic for a built-in logicblock observer operating at 1 Gbit/s and 1.2 V supply

The authors show that merged current switch logic is an excellent candidate for enabling low supply voltages and maintaining an operating speed in the GHz range. The demonstration circuit fabricated in a 0.8 μm BiCMOS process operates at supply voltages as low as 1.2 V with a bit rate of 1 Gbit/s. The dynamic power consumption is 461 μW/gate     

A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP)2)latch and its application in a dual-modulus prescaler

A high speed dual-phase dynamic-pseudo NMOS ((DP)²) latch using clocked pseudo-NMOS inverters is presented. Compared to the conventional D-latch, this circuit has a higher maximum operating frequency and consumes lower dynamic power at a given operating frequency. The latch has been demonstrated by utilizing it in the synchronous counter section of a dual-phase dual-modulus prescaler implemented in a 0.8 μm CMOS process. The maximum operating frequency for the prescaler at 3 V supply voltage is 1.3 GHz, while the power consumption is 9.7 mW. This power consumption is significantly lower than those of the previously reported prescalers implemented in 0.8 μm CMOS processes. The 9.7 mW power consumption at 1.3 GHz also compares favorably to the 24 mW power consumption of the 1.75 GHz prescaler using MOS current mode latches implemented in a 0.7 μm CMOS process. A 25% reduction of the maximum operating frequency for a ~60% reduction of the power consumption should be a useful tradeoff     

高压开关电源开环与闭环特性比较

现研制出紧凑型重复频率的高压开关电源,该电源具有体积小、成本低等优点,设计指标是在70 kΩ负载阻抗上上升沿600 ns,半脉宽15 μs,输出瞬时电压峰值30~210 kV可调且电压正负可转换。采用Matlab/Simulink软件仿真和实验验证高压开关电源开环性能指标,针对开环输出电压难以保持稳定,且难以使开关电极稳定触发的缺点,加入反馈构成闭环系统并利用Pspice软件仿真,可获得稳定输出电压154 kV,达到稳定时间20 μs。通过对高压开关电源开环和闭环系统的计算机仿真结果比较,可得加入反馈系统的高压开关电源具有良好的稳压特性。     

A 0.5-mW passive telemetry IC for biomedical applications

A low-power, single-chip, one-channel, fully implantable microtransponder system for low-frequency biomedical sensor applications is described. The circuit is powered by an external RF source at 27/40 MHz. No battery is required. Wireless communication with external monitoring units is realized by absorption modulation. As the radiated power received by a small coil can be as low as a few milliwatts, the data acquisition/transmission system has been optimized for low power consumption. The system has been integrated in a 2-μm 40-V BiCMOS technology. It includes a low-offset amplifier, a low-pass notch filter, an A/D converter, a voltage doubler/rectifier, as well as a low-power voltage regulator. The implemented switched-capacitor amplifier features 45-μV offset and an integrated noise of 21 μV for a bandwidth of 30 Hz while consuming less than 30 μW power. The digitized sensor data are transmitted as low duty-cycle PPM-AM signals with a rate of 1 kBd. The entire system, including the 1.6-kΩ bridge sensor, consumes only 520 μW, which makes it well suited for long-term monitoring of biomedical signals     

A class-B output buffer for flat-panel-display column driver

Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating voltage range class-B output buffer amplifier for driving the large column line capacitance in a flat-panel display. A comparator is used in the negative feedback path to eliminate quiescent current in the output stage. The proposed output buffer circuit was implemented in a 0.8 μm CMOS process. Its output voltage swing is from 1 V to the supply voltage. With 5 V supply and 600 pF load, the maximum tracking error is ±7 mV. The measured static current is 24 μA. The settling time for 4 V swing to within 0.2% is 8 μs, which is more than adequate for driving 1280×1024 pixels liquid crystal displays with 86 Hz frame rate and 256 gray levels in each color     

A low voltage SRAM for embedded applications

A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 μW. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 μW. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power     

High-speed divide-by-4/5 counter for a dual-modulus prescaler

A new high-speed divide-by-4/5 counter is developed. Based on this divide-by-4/5 counter, a 3 V 2 M ~1.1 GHz dual-modulus divide-by-128/129 prescaler fabricated with 0.6 μm CMOS technology is presented. Its maximum operating frequency of 1.11 GHz with power consumption of 19.2 mW has been measured at a 3 V supply voltage. In addition, for a power supply of 1.5 V, the circuit consumed 2.67 mW at a maximum input frequency of 520 MHz     

A high precision high PSRR bandgap reference with thermal hysteresis protection

To meet the accuracy requirement for the bandgap voltage reference by the increasing data conversion precision of integrated circuits,a high-order curvature-compensated bandgap voltage reference is presented employing the characteristic of bipolar transistor current gain exponentially changing with temperature variations.In addition,an over-temperature protection circuit with a thermal hysteresis function to prevent thermal oscillation is proposed.Based on the CSMC 0.5μm 20 V BCD process,the designed cir...     

Calculation of the soft error rate of submicron CMOS logic circuits

A method to calculate the soft error rate (SER) of CMOS logic circuits with dynamic pipeline registers is described. This method takes into account charge collection by drift and diffusion. The method is verified by comparison of calculated SER's to measurement results. Using this method, the SER of a highly pipelined multiplier is calculated as a function of supply voltage for a 0.6 μm, 0.3 μm, and 0.12 μm technology, respectively. It has been found that the SER of such highly pipelined submicron CMOS circuits may become too high so that countermeasures have to be taken. Since the SER greatly increases with decreasing supply voltage, low-power/low-voltage circuits may show more than eight times the SER for half the normal supply voltage as compared to conventional designs     

一种无运放低压低功耗CMOS带隙基准电压源的设计

采用无运放电路结构,通过改进反馈环路和调整电阻的方法,设计了一种低电压低功耗的带隙基准电压源.相比传统有运放结构,电路芯片面积更小和具有更低的电流损耗,并且大部分电流损耗都用于产生输出电压.基于CSMC 0.5 μmCMOS工艺对所研制带隙基准电压源进行流片,测试结果表明,当电源电压大于0.85 V时,能够产生稳定的输...     

Low-voltage double-sampled ΣΔ converters

An obvious way of achieving higher signal-to-noise ratio in oversampled data converters is by increasing the effective sampling rate. If all other components are kept constant, this translates into integrators with larger bandwidth that in turn results in higher overall power consumption. This work introduces the fully floating switched-capacitor configuration as a simple and robust technique to effectively double the sampling rate of oversampled data converters without compromising any aspect of the performance and yet maintaining the power levels of the conventional approach. The use of internal decimation in the switched-capacitor ladder structure of the digital-to-analog converter further helps in achieving the power budget goals. These converters have been implemented with circuitry capable of operating at a minimum supply voltage of 1.8 V under worst case process and temperature conditions and using clock bootstrapping for the transfer gates. The bootstrapping circuit described here uses a single internal capacitor and has functionality that limits the maximum clock voltage to safe levels under a wide range of supply voltages. The prototype was fabricated in a 0.5-μm CMOS double-poly technology. The analog-to-digital converter occupies a die area of 0.11 mm² dissipating 550 μW while the digital-to-analog converter occupies 0.28 mm² dissipating 600 μW     

Design and characterization of superlattice infrared photodetectoroperating at low bias voltage

In this paper, we investigate the performance and characterization of a 15-period superlattice embedded between two thick AlGaAs barriers. The structure can operate at low bias voltage with less power consumption for 8-10 μm long-wavelength infrared detection. In our design, one barrier is used to reduce the dark current and the other one is designed to enhance the collection efficiency of photoelectrons at the collector contact. The fabricated detector can be operated at a bias voltage lower than 0.1 V and exhibits a pronounced photovoltaic response. The spectral response shows voltage dependence around 0 V. At high bias voltage (>25 mV) the spectral lineshape is independent of bias and is around 8-10 μm with peak wavelength at 9.3 μm. At lower bias voltage the response is shifted toward shorter wavelength range. The peak responsivity was found to be 12 mA/W at λ_p =8.7 μm and zero bias and 85 mA/W at λ_p=9.3 μm and 0.1 V. Background limitation can be achieved up to 65 K with bias voltage less than 0.1 V. The measured noise power spectral density of the dark current at 77 K shows the characteristics of full shot noise rather than generation-recombination noise. The peak detectivity is determined to be D^*=3.5×10⁹ cm√(Hz)/W at 77 K and 0.1 V. In comparison with a conventional 30-period QWIP, our detector has the advantages of better performance at low bias voltages with lower power consumption and a tunable feature of spectral range     

Realisation of exponential V-I converter using composite NMOStransistors

A CMOS voltage-to-current converter with exponential characteristics is presented. The Taylor's series expansion is used for realising the exponential function. In a 0.35 μm CMOS process, the HSPICE simulation results show a 15 dB linear range with a linearity error of <±0.5 dB. The total power consumption is <0.8 mW with ±1.5 V supply voltage. The circuit can be used in the design of a variable gain amplifier (VGA)     

A source-line programming scheme for low-voltage operation NANDflash memories

To realize a low-voltage operation NAND flash memory, a new source-line programming scheme has been proposed. This architecture drastically reduces the program disturbance without circuit area, manufacturing cost, program speed, or power consumption overhead. In order to improve the program disturbance characteristics, a high program inhibit voltage is applied to the channel from the source line, as opposed to from the bit line of the conventional scheme. The bit-line swing is decreased to 0.5 V to achieve a lower power consumption. Although the conventional NAND flash memory cannot operate below 2.0 V due to the program disturbance issue, the proposed NAND flash memory shows excellent program disturbance characteristics irrespective of the supply voltage. A very fast programming of 192 μs/page and a very low power operation of 22 mW at 1.4 V can be realized in the proposed scheme