Mathematical Models of the Common-Source and Common-Gate Amplifiers Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed in this paper. The models are compared against data collected with MFSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth.     

Extended Characterization of the Common-Source and Common-Gate Amplifiers Using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and additional device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation of load, quiescent point, or input signal on each circuit are shown. Advantages and applications of the MFSFET and the circuit performance are discussed.     

DESIGN OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE

ABSTRACT

Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.     

Studies on Al-doped ZnO thin-film transistors with Pb(Zr0.3Ti0.7)O3 gate insulator

We report the fabrication of Al-doped ZnO thin-film transistors (FeFETs) on the ferroelectric Pb(Zr_0.3Ti_0.7)O₃ (PZT) gate insulator for the application of nonvolatile random access memory. The results demonstrate the basic principle of Al-doped ZnO resistive switching between the high and low resistive states upon the polarization switching of ferroelectric layer. Own to the good ferroelectric property and high reliability of PZT, such as fatigue, high speed of signal reading and writing, low coercive electric field, etc., this device has an excellent electrical performance. The memory device exhibits a source-drain current modulation with an ON/OFF current ratio close 10³.     

METAL-FERROELECTRIC-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR NAND GATE SWITCHING TIME ANALYSIS

ABSTRACT

Previous research investigated the modeling of a NAND gate constructed of n-channel Metal-Ferroelectric-Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate.     

Impact of semiconductor/metal interfaces on contact resistance and operating speed of organic thin film transistors

The contact resistance of field effect transistors based on pentacene and parylene has been investigated by experimental and numerical analysis. The device simulation was performed using finite element two-dimensional drift-diffusion simulation taking into account field-dependent mobility, interface/bulk trap states and fixed charge density at the organic/insulator interface. The width-normalized contact resistance extracted from simulation which included an interface dipole layer between the gold source/drain electrodes and pentacene was 91 k??cm. However, contact resistance extracted from the simulation, without consideration of interface dipole was 52.4?k??cm, which is about half of the experimentally extracted 108?k??cm. This indicates that interface dipoles are critical effects which degrade performances of organic field effect transistors by increasing the contact resistance. Using numerical calculations and circuit simulations, we have predicted a 1?MHz switching frequency for a 1???m channel length transistor without dipole interface between gold and pentacene. The transistor with dipole interface is predicted, via the same methods, to exhibit an operating frequency of less than 0.5?MHz.     

Characteristics of lithium niobate based capacitors and transistors

Abstract

The electrical properties of thin film (<1000 Å) capacitor devices of lithium niobate grown on silicon and platinum and of thicker film metal-ferroelectric-semiconductor field effect transistors (MFSFET) with lithium niobate as the gate material were measured. Dielectric constants of the thin films on silicon were as high as 27, while those for films on platinum were as high as 49. The MFSFET structures showed good FET properties, and demonstrated a channel current modulation consistent with switching of the ferroelectric gate by pulsing.     

大功率晶体管脉宽调制直流调速系统

该系统采用电流、速度双闭环的控制结构 ,主电路由大功率晶体管构成H型电路 ,H型电路与控制电路配合可以使电动机的电枢电压频率为大功率晶体管开关频率的 2倍。围绕主电路的控制规律 ,介绍了控制电路中的脉宽调制电路(PWM)、延时电路、驱动电路等电路的实现方法。测试结果表明 ,系统反应快速 ,调速范围宽 ,真正实现转速无静差。     

SiC功率器件的研究和展望

分析了碳化硅(SiC)功率器件的研究现状与发展趋势,给出了在SiC功率整流二极管、SiC功率晶体管以及关键工艺中取得的最新研究成果.研制出了具有较好整流特性的SiC肖特基势垒二极管,并对其输运机理和高温特性进行了研究.研制成功了国内第一个SiC MPS二极管,耐压高达600V,正向电压为3.5V时电流密度可达1 000A/cm2.研制出国内第一个SiC MOSFET和第一个SiC BCMOSFET.所制备的SiC BCMOSFET可得到最高为90 cm2/(V·S)的有效迁移率.分析了界面态电荷和界面粗糙对SiC MOSFET反型层迁移率的影响,其结果对提高SiC MOSFET器件特性有一定指导作用.     

Analysing the operation of the basic pass transistor structure

Pass transistor logic has become important for the design of low‐power high‐performance digital circuits due to the smaller node capacitances and reduced transistors count it offers. However, the acceptance and application of this logic depends on the availability of supporting automation tools, e.g. timing simulators, that can accurately analyse the performance of large circuits at a speed, significantly faster than that of SPICE based tools. In this paper, a simple and robust modelling technique for the basic pass transistor structure is presented, which offers the possibility of fast timing analysis for circuits that employ pass transistors as controlled switches. The proposed methodology takes advantage of the physical mechanisms in the pass transistor operation. The obtained accuracy compared to SPICE simulation results is sufficient for a wide range of input and circuit parameters. Copyright © 2006 John Wiley & Sons, Ltd.     

I-V characteristics of a ferroelectric field effect transistor

Abstract

There are many possible uses for ferroelectric field effect transistors. To understand their application, a fundamental knowledge of their basic characteristics must first be found. In this research, the current and voltage characteristics of a FFET are described from empirical data. The effective gate capacitance and charge are derived from experimental data on an actual ferroelectric transistor. A general equation ^[1] for a MOSFET is used to derive the internal characteristics of the transistor. Experimental data derived from a Radiant Technologies^[2] FFET is used to calculate the internal transistor characteristics using fundamental MOSFET equations.

The drain current was measured under several different gate and drain voltages and with different initial polarizations on the ferroelectric material. Two polarization conditions were used. One with the gate ferroelectric material polarized with a +9.0 volt write pulse and one with a -9.0 volt pulse. The transistor is also simulated using a mathematical model from earlier research ^[3]. This model accurately predicts the I-V characteristics of the transistor.     

Full-band particle-based simulation of 85 nm AlInSb/InSb quantum well transistors

In this work, Indium Antimonide (InSb) quantum well transistors are investigated using full-band Cellular Monte Carlo simulations. Both Depletion and Enhancement transistors are simulated, the latter being modeled using a deep recess gate. The steady-state characteristics of the devices are analyzed showing an average sub-threshold slope of 326 mV/dec and a DIBL of 569 mV/V. The small-signal behavior of the depletion and enhancement mode transistors is also investigated, and an average cut-off frequency of 380 GHz is computed. Finally, a comparison is performed between the different transistors showing all the advantages of the deep recess gate configuration such as a better sub-threshold slope and cutoff frequency.     

A drain current model for Schottky-barrier CNT-FETs

We present here a physics-based drain current model for Schottky-barrier carbon nanotube field-effect transistors. The model captures a number of features exhibited by these transistors such as thermionic and tunnel emission, ambipolar conduction, ballistic transport, multimode propagation and electrostatics dominated by the nanotube capacitance     

Modelling CoolMOSC3 transistor characteristics in SPICE

In this paper three models of CoolMOSC3 transistors worked out by Infineon Technologies, dedicated for SPICE, are presented and investigated. These models are verified experimentally both for dc and ac device operating conditions. The advantages and drawbacks of the investigated models are shown and discussed. The device operating conditions, at which the models are of acceptable accuracy, are identified. Copyright © 2009 John Wiley & Sons, Ltd.     

Three-dimensional simulation for negative resistance characteristics of parasitic bipolar transistor in a small-sized mosfet structure

The behaviours of parasitic bipolar transistors are investigated by exploring the physical mechanisms of negative resistance characteristics generated in a small-sized MOSFET structure. Physical experiments and three-dimensional simulations verify the expected negative resistance characteristics. The effects of variations of device parameters such as injected substrate current levels, doping concentrations, channel widths, and physical device sizes are investigated by simulation. According to simulation results, the operation of a parasitic bipolar transistor is initiated by the injected substrate current; this explains the negative resistance characteristics occurring at low operating voltages.     

基于电光晶体的激光PPM偏振调制设计

调制解调技术是大气激光通信系统中的关键技术。提出一种新的光与电脉冲组合调制方式,对已经进行过PPM（脉冲位置调制）调制的激光信号再用电光晶体进行偏振调制。设计了同一信道四种偏振态（0°、30°、60°和90°方向振动的偏振光束）的PPM偏振调制方案。搭建了硬件时序电路及偏振调制系统,四束偏振光通过同一大气信道,同时被衰减,信道的衰减可以相互抵消。硬件仿真结果表明：采用光与电脉冲组合调制方式可以减少甚至消除大气信道对大气激光通信的影响,而且由于光波的偏振复用可以成倍提高大气激光通信的通信容量。     

Electronic model of a Ferroelectric Field Effect transistor

Abstract

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. The input and output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and are compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.     

Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

In this paper, a new highly linear operational transconductance amplifier (OTA) based on triode‐mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode‐mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo‐differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low‐power linear Gm‐C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp‐p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18‐μ m CMOS technology with Hspice simulator. Copyright © 2017 John Wiley & Sons, Ltd.     

The Effect of Gate-Bias Stress and Temperature on the Performance of ZnO Thin-Film Transistors

The stability of ZnO thin-film transistors is investigated by using gate-bias stress. It is found that the application of positive and negative stress results in the device transfer characteristics shifting in positive and negative directions, respectively. It is postulated that this device instability is a consequence of charge trapping at or near the channel/insulator interface. In addition, there is a degradation of subthreshold behavior and channel mobility, which is suggested to result from the defect-state creation within the ZnO layer. The effect of elevated temperature stress shows a predominance of interface-state creation in comparison to trapping under gate-bias stress. Device instability appears to be a consequence of the charging and discharging of preexisting trap states at the interface and in the channel region of the devices. All stressed devices recover their original characteristics after a short period at room temperature without the need for any thermal or bias annealing.     

基于LCD的晶体管特性曲线图示仪

本文提出了一种在LCD上显示晶体管输出特性曲线的方法,并设计制作了晶体管特性曲线图示仪。该仪器不但能显示NPN、PNP、FET等晶体管的输入、输出特性曲线,并能在屏幕上直接显示HFE值,也可以通过串行口将测试结果传给PC机作为资料存档。在硬件设计上,充分利用了AVRmega16单片机的I/O引脚和片内外设,使仪器简化了电路,降低了成本。在软件设计上,采用数字滤波,使仪器达到了较高的精度,在特定的场合可以取代贵重的专业测试设备在广大电子工作者中得到应用。