Textural and microstructural transformation of Cu damascene interconnects after annealing

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.     

Three-dimensional simulation of microstructure evolution in damascene interconnects: Effect of overburden thickness

Microstructure in the damascene interconnects evolves with the overburden layer, an excessive metal layer over trenches. We present the results of three-dimensional simulation, which show the effects of overburden thickness on microstructure evolution in a trench. When the thickness of the overburden is less than half of the trench depth, for a trench with the aspect ratio of unity, the microstructure in the trench tends to evolve into a bamboo structure. This effect is discussed in terms of grain sizes in the trench and those in the overburden. The thinner overburden layer would have smaller grains, of which growth is limited by its thickness. Such small-sized grains in the overburden are not likely to grow into the trench, which hardly make grain boundaries in the trench. Meanwhile, the grains from the trench are able to continue growth inside the trench, resulting in a bamboo structure. Overburden thickness affects the reliability and the electrical performance of the damascene copper interconnects. Optimization of overburden thickness is required to minimize these effects.     

Correlation of electromigration lifetime distribution to failure mode in dual Damascene Cu/SiLK interconnects

The electromigration cumulative percent lifetime probability of dual Damascene Cu/SiLK interconnects was fitted using three, individual lognormal functions where the functional populations were grouped by void growth location determined from focused ion beam failure analysis of all 54 of the stressed structures. The early, first mode failures were characterized by small voids in the bottom of the vias. The intermediate mode failures had voids in the line and via bottom while the late mode failures had voids that formed in the line only. The three, individual lognormal functions provided good fits of the data. Failure mode population separation using comprehensive failure analysis suggested that only the first mode failures should be used in the prediction of the chip design current.     

铜互连线静水应力的有限元模拟

本文根据工业上使用的铜大马士革互连线尺寸建立了三维有限元模型,模拟计算了铜大马士革互连线中对应力诱导形成空洞很关键的静水应力分布,对比分析了不同低k介质、阻挡层材料和互连线深宽比对静水应力的影响。研究结果表明,静水应力受k介质、阻挡层材料和互连线深宽比影响很大,静水应力在铜大马士革互连线中分布不均匀且最大应力出现在互连线表面。     

大马士革铜互连线织构的研究

采用EBSD研究了不同线宽和退火前后Cu互连线的织构和晶界特征分布.Cu互连线均具有多重织构,其中(111)织构强度最高.沉积态样品在室温下发生了自退火现象,并出现了一些异常长大的晶粒.随高宽比降低和退火处理,Cu互连线晶粒尺寸变大,(111)织构得到加强,而具有较低应变程度的织构与(111)织构强度的比例下降.沉积态样品出现了(111)<112>和(111)<231>织构组分.退火后,出现了(111)<110>组分,而且(111)<112>和(111)<231>组分得到增强.Cu互连线以大角度晶界为主,其中具有55°～60°错配角的晶界和∑3晶界比例最高,35°～40°的错配角和∑9晶界次之.随高宽比增加和退火处理,∑3晶界比例逐渐升高,∑9晶界比例下降.     

大马士革铜互连线织构的研究

采用EBSD研究了不同线宽和退火前后Cu互连线的织构和晶界特征分布.Cu互连线均具有多重织构,其中(111)织构强度最高.沉积态样品在室温下发生了自退火现象,并出现了一些异常长大的晶粒.随高宽比降低和退火处理,Cu互连线晶粒尺寸变大,(111)织构得到加强,而具有较低应变程度的织构与(111)织构强度的比例下降.沉积态样品出现了(111)<112>和(111)<231>织构组分.退火后,出现了(111)<110>组分,而且(111)<112>和(111)<231>组分得到增强.Cu互连线以大角度晶界为主,其中具有55°～60°错配角的晶界和∑3晶界比例最高,35°～40°的错配角和∑9晶界次之.随高宽比增加和退火处理,∑3晶界比例逐渐升高,∑9晶界比例下降.     

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress,which is critical to the formation of stress-induced voiding(SIV) in copper damascene interconnects.Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry.In addition,hydrostatic stress is studied through the influences of different low-k dielectrics,barrier layers and line widths of copper lines,and the results indicate that hydrostatic stress is strongly dependent on these factors.Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.     

Characterization and optimization of copper chemical mechanical planarization

The feature scale planarization of the copper chemical mechanical planarization (CMP) process has been characterized for two copper processes using Hitachi 430-TU/Hitachi T605 and Cabot 5001/Arch Cu10K consumables. The first process is an example of an abrasive-free polish with a high-selectivity barrier slurry, while the second is an example of a conventional abrasive slurry with a low-selectivity barrier slurry. Copper fill planarization has been characterized for structures with conformal deposition as well as with bumps resulting from bottom-up fill. Dishing and erosion were characterized for several structures after clearing. The abrasive-free polish resulted in low sensitivity to overpolish and low saturation levels for dishing and erosion. Consequently, this demonstrated superior performance when compared to the International Technology Roadmap for Semiconductors (ITRS) 2000 roadmap targets for planarization. While the conventional slurry could achieve the 0.13-μm technology node requirements, the abrasive-free polish met the planarization requirements beyond the 0.10-μm technology node.     

Physical investigation of the impact of electrolessly deposited self-aligned caps on insulation of copper interconnects

With the miniaturization of ULSI circuits and the associated increase of current density up to several MA/cm², copper interconnects are facing electromigration issues at the top interface with the dielectric capping layer SiC(N). A promising solution is to insert selectively on top of copper lines a CoWP metallic self-aligned encapsulation layer, deposited using a wet electroless process. We study the impact of this process on electrical line insulation as a function of cap thickness at the 65 nm technology node and we investigate the physical origin of leakage currents. Below a critical thickness, only a slight leakage current increase of less than one decade is observed, remaining within the specification for self-aligned capping layer processes. Above this critical thickness, large leakage currents are generated due to the combined effect of lateral growth and the presence of parasitic redeposited nodules. We show that a simple phenomenological model allows to reproduce the experimental data, to assess quantitatively the contribution of parasitic defects, and to predict that the self-aligned barrier technology should be extendible up to the 32 nm node, provided that a thin cap layer of less than 8 nm is used.     

Ion beam preparation of passivated copper integrated circuit structures for electron backscatter diffraction/orientation imaging microscopy analysis

Passivation layers were removed from copper interconnect lines using a broad beam ion source in preparation for electron backscatter diffraction (EBSD) and orientation imaging microscopy (OIM) analysis. Results were obtained on interconnect lines with widths as small as 0.25 μm. The effects of ion beam energy and scanning electron microscope (SEM) acceleration voltage on the quality of the results obtained are examined and explained. The use of thin amorphous carbon coatings to reduce specimen charging during orientation data collection is also discussed.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

Innovative wire bonding method using a chemically reacted thin layer for chips with copper interconnects

This paper presents a novel method in which an oxide film is used to facilitate the thermosonic wire bonding of gold wire onto copper pads. A cuprous oxide film is generated by controlling the pH values of the chemical solution. Compared to cupric oxide films, the cuprous oxide film is denser and more brittle and therefore facilitates the bonding process without the need for the elaborate procedures and equipment required by more conventional wire bonding methods.     

Microstructural characterization of inlaid copper interconnect lines

The microstructure of inlaid Cu lines has been quantified as a function of annealing conditions, post-plating, and post-CMP. The grain size distribution was measured using the median intercept method, crystallographic texture was characterized by pole figure analysis, and mechanical stress was determined using x-ray diffraction. The median grain size and mechanical stress level increase with increasing anneal temperature. The crystallographic texture is independent of the anneal temperature and is predominantly (111) with a small fraction of sidewall-nucleated (111) grains. The (111) grains nucleated from the trench bottom have a preferred in-plane orientation. The grain growth in the trench is independent of that in the overburden.     

Grain nucleation and texture analysis of electroless copper deposition on a palladium seed layer

Electroless copper grains were deposited on a Pd seed layer under varying bath conditions. The seed layer was determined to have a (111) texture using grazing incident x-ray (GIX) diffraction. Multiple nucleation sites in the grain boundaries were imaged using a scanning tunneling microscope. Continual copper growth produced row-like structures. The texture of the electrolessly deposited copper (ED-Cu) grains were determined to be (111). No radial grain orientation for the Pd seed layer or the ED-Cu thin film was detected using GIX diffraction. Atomic force microscope images indicated continual Cu nucleation throughout the deposition process. PdH was formed as a by-product of the electroless deposition process, and detected by x-ray diffraction.     

Direct sub-100-nm patterning of an organic low-k dielectric for electrical and optical interconnects

Low-k dielectric materials compatible with copper interconnect fabrication processes extending to the sub-50-nm technology nodes are desired for high speed integrated circuit (IC) fabrication. We demonstrate that bisbenzocyclobutene (BCB), an organic low-k dielectric material, can be patterned with sub-100-nm resolution using electron beam lithography, providing new avenues for nanoscale electrical and optical interconnect fabrication.     

Emerging interconnects: a state-of-the-art review and emerging solutions

Aluminium was a primary material for interconnection in integrated circuits (ICs) since their inception. Later, copper was introduced as interconnect material which has better metallic conductivity and resistance to electromigration. As the aggressive technology scaling continues, the copper resistivity increased because of size effects, which causes increase in delay, power dissipation and electromigration. The need to reduce the resistor-capacitor??????? delay, dynamic power utilisation and the crosstalk commotion is as of now the fundamental main impetus behind the presentation of new materials. The purpose of this paper is to do a survey of interconnect material used in IC from introduction of ICs to till date. This paper studies and reviews new materials available for interconnect application which are optical interconnects, carbon nanotube (CNT), graphene nanoribbons (GNRs) and silicon nanowires which are alternatives to copper. While doing a survey of interconnect material, it is found that multiwalled CNTs, multilayer GNR and mixed CNT bundles are promising candidates and are ultimate choice that can strongly address the problems faced by copper but on integration basis copper would last for coming years.     

磁控溅射Cu膜的织构与残余应力

用磁控溅射工艺在不同沉积温度制备200 nm与2μm厚的Cu膜,并用X射线衍射仪(XRD)与光学相移方法测量薄膜织构与残余应力.结果表明,对于200 nm厚Cu膜,随着沉积温度T增加,晶粒取向组成几乎保持不变,薄膜具有较低拉应力且不断减小;而对于2μm厚Cu膜,随着T增加,Cu<111>/Cu<200>晶粒取向组成比值急剧减小.薄膜具有较大的拉应力且不断减小.根据表面能、应变能及缺陷形成等机制对薄膜残余应力与织构的演化特征进行了分析.     

Texture characterization of Cu interconnects with different Ta-based sidewall diffusion barriers

X-ray diffraction is used to assess the texture of narrow lines and study the impact of different sidewall diffusion barrier materials. All the Ta-based barriers developed a strong 〈1 1 1〉 texture in the scaled geometry, with little effect from sidewall growth. Comparisons were made with blanket wafers, demonstrating the pined grain structure in the narrow lines and contrasting change in texture due to re-crystallization in the unconstrained film. Furthermore, patterned lines showed significant anti-symmetric plane distribution influenced by high strains and twinning along the lines.     

Atomic layer chemical vapour deposition of copper

Copper films with (1 1 1) texture are of crucial importance in integrated circuit interconnects. We have deposited strongly (1 1 1)-textured thin films of copper by atomic layer deposition (ALD) using [2,2,6,6-tetramethyl-3,5-heptadionato] Cu(II), Cu(thd)₂, as the precursor. The dependence of the microstructure of the films on ALD conditions, such as the number of ALD cycles and the deposition temperature was studied by X-ray diffraction, scanning electron microscopy (SEM), and transmission electron microscopy. Analysis of (1 1 1)-textured films shows the presence of twin planes in the copper grains throughout the films. SEM shows a labyrinthine structure of highly connected, large grains developing as film thickness increases. This leads to low resistivity and suggests high resistance to electromigration.