All-IP 4G Network architecture for efficient mobility and resource management

In this article, we investigate 4G network architecture and consider two underlying layers: PHY and MAC. We compare two models of wireless access network: pure all-IP and subnet based networks. The pure all-IP model is simple and cost-efficient but causes implementation issues of mobility management and resource coordination. In contrast, the subnet based network enables layer 2 and layer 3 handoffs to be executed independently, deploying several access points under an access router. Further, to handle various cases efficiently according to traffic class and mobility, we present an advanced model of a hierarchical cellular system that combines multiple access techniques of OFDMA and FH-OFDMA with microcells and macrocells. Finally, as an integrated approach to support diverse QoS requirements, we consider an IP-triggered resource allocation strategy (ITRAS) that exploits IntServ and DiffServ of the network layer to interwork with channel allocation and multiple access of MAC and PHY layers, respectively. These cross layer approaches shed light on designing a QoS support model in a 4G network that cannot be handled properly by a single layer based approach     

A novel and efficient routing architecture for multi-FPGA systems

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and field-programmable interconnect devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed, and previous research has shown that the partial crossbar is one of the best existing architectures. In this paper, we propose a new routing architecture, called the hybrid complete-graph and partial-crossbar (HCGP) which has superior speed and cost compared to a partial crossbar. The new architecture uses both hard-wired and programmable connections between the FPGAs. We compare the performance and cost of the HCGP and partial crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. A customized set of partitioning and interchip routing tools were developed, with particular attention paid to architecture-appropriate interchip routing algorithms. We show that the cost of the partial crossbar (as measured by the number of pins on all FPGAs and FPIDs required to fit a design), is on average 20% more than the new HCGP architecture and as much as 25% more. Furthermore, the critical path delay for designs implemented on the partial crossbar were on average 20% more than the HCGP architecture and up to 43% more. Using our experimental approach, we also explore a key architecture parameter associated with the HCGP architecture-the proportion of hard-wired connections versus programmable connections-to determine its best value     

An efficient parallel architecture for ray-tracing

Real time rendering of three-dimensional scenes in high photorealistic details is a hard task, such as in the ray tracing rendering algorithm. In general, the performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. However, parallel implementations of ray tracing have been enabling reasonable real time performance, as the algorithm is embarrassingly parallel. Thus, a custom parallel design in hardware is likely to achieve an even higher performance. In this paper, we propose a hardware parallel architecture capable of dealing with the main desirable features of ray tracing, such as shadows and reflection effects, imposing low area cost and a promising rendering performance. Such architecture, called GridRT, is based on the Uniform Grid acceleration structure and is intended to deliver massive parallelism through parallel ray-triangle intersection tests as well as parallel processing of many rays. A hardware implementation of the proposed architecture is presented, together with some performance results and resources requirements. The rendering is reduced by 80% using a grid configuration of eight processing elements.     

PARE: instruction set architecture for efficient code sizereduction

To achieve efficient code size reduction, a new instruction set architecture and a register allocation technique optimised for the architecture are proposed. Experiments show that the efficiency of the code size reduction is improved by an average of 13.8% when compared with that of the conventional approach     

An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

A highly efficient residue-combinatorial architecture for digital filters

A hybrid digital filter structure is presented that combines a combinatorial multiplication technique with a residue number architecture. The hybrid technique eliminates general multiplication and results in a parallel structure inherent in the residue number system. Results indicate that better speed/cost ratios can be obtained with the hybrid architecture than with either structure alone for applications in which high performance is a predominant factor.     

Energy efficient hybrid adder architecture

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.     

Service-oriented mobility management architecture for seamless handover in ubiquitous networks

In ubiquitous wireless LANs, a mobile node is likely to move between many access points while using certain applications. However, in the conventional Internet architecture, an MN can never inherently avoid the degradation in communication quality during handover. To achieve seamless handover, we propose a service-oriented mobility management scheme to address application quality. In this article, we first clarify three requirements for achieving seamless handover. We then describe our concept of the service-oriented mobility management scheme, which satisfies all three requirements. Our main contribution is the proposal of a scheme of how to properly use the number of frame retransmissions as a new handover-decision criterion to accomplish seamless handover. Performance evaluations show that our proposed scheme can maintain application quality during handover     

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

In this paper, an efficient very large scale integration (VLSI) architecture, called flipping structure, is proposed for the lifting-based discrete wavelet transform. It can provide a variety of hardware implementations to improve and possibly minimize the critical path as well as the memory requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. The precision issues are also analyzed. By case studies of the JPEG2000 default lossy (9,7) filter, an integer (9,7) filter, and the (6,10) filter, the efficiency of the proposed flipping structure is demonstrated.     

The arrayed-waveguide grating-based single-hop WDM network: an architecture for efficient multicasting

Research on multicasting in single-hop wavelength-division-multiplexing (WDM) networks has so far focused on networks based on the passive star coupler (PSC), a broadcast device. It has been shown that multicasting performance is improved by partitioning multicast transmissions into multiple multicast copies. However, the channel bottleneck of the PSC, which does not allow for spatial wavelength reuse, restricts the multicast performance. We investigate multicasting in a single-hop WDM network that is based on an arrayed-waveguide grating (AWG), a wavelength routing device that allows for spatial wavelength reuse. In our network, optical multicasting is enabled by wavelength-insensitive splitters that are attached to the AWG output ports. Multicasts are partitioned among the splitters and each multicast copy is routed to a different splitter by sending it on a different wavelength. We demonstrate that the spatial wavelength reuse in our network significantly improves the throughput-delay performance for multicast traffic. By means of analysis and simulations, we also demonstrate that, for a typical mix of unicast and multicast traffic, the throughput-delay performance is dramatically increased by transmitting multicast packets concurrently with control information in the reservation medium access control protocol of our AWG-based network.     

An efficient and flexible architecture for high-density gate arrays

The authors describe an efficient and flexible HDGA (high-density gate array) architecture (or sea of transistors) with cells containing three common-gate wide and small transistors on which both logic and memory functions can be relatively densely mapped. The use of titanium-silicide straps for local interconnect (as an alternative to the third metal layer) is evaluated through different designs. The design and performance of an experimental chip in 0.8-μm CMOS technology are discussed. In a comparison of many different standard-cell and common-gate HDGA designs, the HDGA implementations showed equal performance at comparable or even smaller chip areas     

AVS插值算法的一种高效的硬件结构设计与实现

提出了AVS解码系统中帧间运动补偿插值算法的一种面向FPGA/ASIC的硬件结构设计.阐述了插值过程的各功能单元的结构,给出了仿真结果及硬件规模.结果表明本文提出的结构设计支持720×576,4:2:0,30FPS的视频在54MHz最低工作频率下的实时解码,是一种适合于集成的高效并行VLSI结构设计.     

An efficient multistage switching node architecture for broadband ISDNs

This paper proposes and analyses a new and efficient multistage switching node architecture for high‐speed communication networks such as Broadband Integrated Services Digital Networks (BISDNs). The proposed architecture has several superior features as compared to the existing switching nodes based on Banyan architecture. The architecture uses a reduced number of stages in an attempt to reduce the delay. Each switching element has its own input buffer and that reduces the blocking probability. Performance of the proposed architecture has been evaluated using simulation. The performance results are presented in the form of utilization, and delay, with different buffer sizes. The results show that the proposed architecture provides better performance in terms of reduced delay and higher throughput. This revised version was published online in June 2006 with corrections to the Cover Date.     

Protocol and architecture supports for network mobility with QoS-handover for high-velocity vehicles

The evolution of wireless access technologies has led to a new era of mobile Internet for high-velocity vehicles. Network mobility is particularly suitable for vehicles because it considers the mobility of an entire network. Vehicles perform handover frequently thus efficient handover is essential to meet the QoS requirements for real-time communications. For high-velocity vehicles, the time constraint is even stricter and the Doppler Effect increases the transmission error rate that both add challenges in mobility management. In this paper, we propose a cross-layer hierarchical network mobility framework called Hi-NEMO for all-IP networks. The advantage of Hi-NEMO is no extra triangular route between a mobile network node and the correspondent node. The design is resilient to error-prone transmission, and protocol-supports fast QoS provisioning in the network mobility service domain. Intensive simulation results demonstrate that Hi-NEMO reduces handover latency as well as packet loss, and supports handover requirements in high-velocity vehicles.     

An efficient bit-serial FIR filter architecture

A new bit-serial architecture for implementation of high order FIR filters is introduced, as well as example FPGA and CMOS realizations. This structure exploits the simplicity of coefficients that consist of two power-of-two terms to yield efficient implementations. Quantization effects are discussed and a simple block scaling method for reducing rounding and truncation noise in high order filters is also presented.This research is supported by the Office of Naval Research under Grant N00014-89-J1327, NSF Grant ECS87-13598, by an AT&T Bell Laboratories Graduate Fellowship, and by University of Kansas General Research allocation 3775-20-0038. Portions of this work were presented at ICASSP-90 in Albuquerque, New Mexico.     

A network-assisted flow mobility architecture for optimized mobile medical multimedia transmission

A large part of mobile Health (mHealth) use-cases such as remote patient monitoring/diagnosis, teleconsultation, and guided surgical intervention requires advanced and reliable mobile communication solutions to provide efficient multimedia transmission with strict medical level Quality of Service (QoS) and Quality of Experience (QoE) provision. The increasing deployment of overlapping wireless access networks enables the possibility to offer the required network resources for ubiquitous and pervasive mHealth services. To address the challenges and support the above use-cases in today’s heterogeneous network (HetNet) environments, we propose a network-assisted flow-based mobility management architecture for optimized real-time mobile medical multimedia communication. The proposed system is empirically evaluated in a Pan-European HetNet testbed with multi-access Android-based mobile devices. We observed that the proposed scheme significantly improves the objective QoE of simultaneous real-time high-resolution electrocardiography and high-definition ultrasound transmissions while also enhances traffic load balancing capabilities of wireless architectures.     

A novel switching architecture for ATM networks

It is known that the flexibility and capacity of asynchronous transfer mode (ATM) networks can meet the bandwidth requirements of multimedia applications. In ATM networks, switching is one of the major bottlenecks of end-to-end communication. We propose using a multiple partitionable circular bus network (MPCBN) as an ATM switch. Connection requests are first transformed into a graph where vertices and edges represent connection requests and conflicts among connection requests, respectively. We then use a graph traversal algorithm to select a maximal set of requests for execution in physically partitioned buses. An approach of using finite projective planes is then used to reduce the number of switch points from O(N²) to O(N √N), where N is the number of ports of a switch. A performance evaluation for both uniform and bursty data sources shows that the approach of using finite projective planes to reduce the number of switch points results in a small increase of cell loss probability     

Design and analysis of an IEEE 802.21-based mobility management architecture: a context-aware approach

Broadband wireless technologies will soon become an integral part of daily life. In this paper we present the design rationale of a context-aware mobility management architecture for seamless handover in heterogeneous networks. Our proposal is a new cross-layer and interactive approach to seamless handover of users and their services. We present a simple though effective analytical model in typical deployment scenarios in heterogeneous networks with the use of the IEEE Media Independent Handover services. Such analytical model is used to evaluate the resulting handover delay when deploying common mobility protocols in our architecture, such as Mobile IP, Hierarchical MIP, and Proxy MIP.     

An efficient algorithm and systolic architecture for multiplechannel adaptive filtering

A multiple-input-multiple-output orthogonalization algorithm and its efficient systolic implementation are presented. The processing architecture is developed using a basic two-input-two-output decorrelation processing element as the primitive building block. Its features are discussed and compared to the approach of K. Gerlach and F.A. Studer (see ibid., vol.AP-34, no.3, p.458-462, 1986) which is based on the modified Gram-Schmidt (MGS) orthogonalization procedure. For simplicity of illustration in the development, batch processing is emphasized. The main features of the newly developed multiple-channel orthogonalization architecture are: (1) it requires no broadcasting of data and any given processing node in the structure only communicates with its neighboring nodes in pipelining fashion; (2) in terms of the total number of arithmetic operations, it is at least as efficient as the MGS approach; (3) the new architecture is developed in a systematic and bottom-up fashion; (4) it is an extremely regular and compact processing structure; (5) no unscrambling of the output channels is needed; and (6) the architecture presented places no restriction on the number of input channels