All-IP 4G Network architecture for efficient mobility and resource management

In this article, we investigate 4G network architecture and consider two underlying layers: PHY and MAC. We compare two models of wireless access network: pure all-IP and subnet based networks. The pure all-IP model is simple and cost-efficient but causes implementation issues of mobility management and resource coordination. In contrast, the subnet based network enables layer 2 and layer 3 handoffs to be executed independently, deploying several access points under an access router. Further, to handle various cases efficiently according to traffic class and mobility, we present an advanced model of a hierarchical cellular system that combines multiple access techniques of OFDMA and FH-OFDMA with microcells and macrocells. Finally, as an integrated approach to support diverse QoS requirements, we consider an IP-triggered resource allocation strategy (ITRAS) that exploits IntServ and DiffServ of the network layer to interwork with channel allocation and multiple access of MAC and PHY layers, respectively. These cross layer approaches shed light on designing a QoS support model in a 4G network that cannot be handled properly by a single layer based approach     

A novel and efficient routing architecture for multi-FPGA systems

Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and field-programmable interconnect devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed, and previous research has shown that the partial crossbar is one of the best existing architectures. In this paper, we propose a new routing architecture, called the hybrid complete-graph and partial-crossbar (HCGP) which has superior speed and cost compared to a partial crossbar. The new architecture uses both hard-wired and programmable connections between the FPGAs. We compare the performance and cost of the HCGP and partial crossbar architectures experimentally, by mapping a set of 15 large benchmark circuits into each architecture. A customized set of partitioning and interchip routing tools were developed, with particular attention paid to architecture-appropriate interchip routing algorithms. We show that the cost of the partial crossbar (as measured by the number of pins on all FPGAs and FPIDs required to fit a design), is on average 20% more than the new HCGP architecture and as much as 25% more. Furthermore, the critical path delay for designs implemented on the partial crossbar were on average 20% more than the HCGP architecture and up to 43% more. Using our experimental approach, we also explore a key architecture parameter associated with the HCGP architecture-the proportion of hard-wired connections versus programmable connections-to determine its best value     

PARE: instruction set architecture for efficient code sizereduction

To achieve efficient code size reduction, a new instruction set architecture and a register allocation technique optimised for the architecture are proposed. Experiments show that the efficiency of the code size reduction is improved by an average of 13.8% when compared with that of the conventional approach     

An efficient parallel architecture for ray-tracing

Real time rendering of three-dimensional scenes in high photorealistic details is a hard task, such as in the ray tracing rendering algorithm. In general, the performance achieved by a sequential software-based implementation of ray tracing is far from satisfactory. However, parallel implementations of ray tracing have been enabling reasonable real time performance, as the algorithm is embarrassingly parallel. Thus, a custom parallel design in hardware is likely to achieve an even higher performance. In this paper, we propose a hardware parallel architecture capable of dealing with the main desirable features of ray tracing, such as shadows and reflection effects, imposing low area cost and a promising rendering performance. Such architecture, called GridRT, is based on the Uniform Grid acceleration structure and is intended to deliver massive parallelism through parallel ray-triangle intersection tests as well as parallel processing of many rays. A hardware implementation of the proposed architecture is presented, together with some performance results and resources requirements. The rendering is reduced by 80% using a grid configuration of eight processing elements.     

An efficient architecture for fault-tolerant ATM switches

A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand     

A highly efficient residue-combinatorial architecture for digital filters

A hybrid digital filter structure is presented that combines a combinatorial multiplication technique with a residue number architecture. The hybrid technique eliminates general multiplication and results in a parallel structure inherent in the residue number system. Results indicate that better speed/cost ratios can be obtained with the hybrid architecture than with either structure alone for applications in which high performance is a predominant factor.     

基于并行处理的一种新型有效的网络架构 BSN-MOT

摘 要：结合BSN及MOT架构的双重优势,提出一种新型的双层架构体系BSN-MOT(mesh of tree),并研究了其上的拓扑性质及在并行处理中应用的基本的通信操作算法。算法包括行、列树广播、单向广播、数据求和、矩阵乘积、最短路径路由及多项式求根。最后,本文通过与其他2种有效的树形双层网络架构Multi-Mesh of trees(MMT)及OMULT比较说明,基于BSN-MOT架构的通信算法要比其他2种网络有着更小些的时间复杂度,且BSN-MOT是一种更具有竞争力的体系结构形式。     

An efficient implementation architecture for wide-band digital downconversion

The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution to the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture.     

Energy efficient hybrid adder architecture

An energy efficient adder design based on a hybrid carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with combining low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, it is optimally repeated. The adder is enhanced in a tree-like structure for further acceleration. 32, 64 and 128-bit adders targeting 500 MHz and 1 GHz clock frequencies were designed in 65 nm technology. They consumed 11–18% less energy compared to adders generated by state-of-the-art EDA synthesis tool.     

Service-oriented mobility management architecture for seamless handover in ubiquitous networks

In ubiquitous wireless LANs, a mobile node is likely to move between many access points while using certain applications. However, in the conventional Internet architecture, an MN can never inherently avoid the degradation in communication quality during handover. To achieve seamless handover, we propose a service-oriented mobility management scheme to address application quality. In this article, we first clarify three requirements for achieving seamless handover. We then describe our concept of the service-oriented mobility management scheme, which satisfies all three requirements. Our main contribution is the proposal of a scheme of how to properly use the number of frame retransmissions as a new handover-decision criterion to accomplish seamless handover. Performance evaluations show that our proposed scheme can maintain application quality during handover     

Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform

In this paper, an efficient very large scale integration (VLSI) architecture, called flipping structure, is proposed for the lifting-based discrete wavelet transform. It can provide a variety of hardware implementations to improve and possibly minimize the critical path as well as the memory requirement of the lifting-based discrete wavelet transform by flipping conventional lifting structures. The precision issues are also analyzed. By case studies of the JPEG2000 default lossy (9,7) filter, an integer (9,7) filter, and the (6,10) filter, the efficiency of the proposed flipping structure is demonstrated.     

The arrayed-waveguide grating-based single-hop WDM network: an architecture for efficient multicasting

Research on multicasting in single-hop wavelength-division-multiplexing (WDM) networks has so far focused on networks based on the passive star coupler (PSC), a broadcast device. It has been shown that multicasting performance is improved by partitioning multicast transmissions into multiple multicast copies. However, the channel bottleneck of the PSC, which does not allow for spatial wavelength reuse, restricts the multicast performance. We investigate multicasting in a single-hop WDM network that is based on an arrayed-waveguide grating (AWG), a wavelength routing device that allows for spatial wavelength reuse. In our network, optical multicasting is enabled by wavelength-insensitive splitters that are attached to the AWG output ports. Multicasts are partitioned among the splitters and each multicast copy is routed to a different splitter by sending it on a different wavelength. We demonstrate that the spatial wavelength reuse in our network significantly improves the throughput-delay performance for multicast traffic. By means of analysis and simulations, we also demonstrate that, for a typical mix of unicast and multicast traffic, the throughput-delay performance is dramatically increased by transmitting multicast packets concurrently with control information in the reservation medium access control protocol of our AWG-based network.     

A novel architecture of Proxy‐LMA mobility management scheme for software‐based smart factory networking

Mobile users expect a network service, in which seamless handoff occurs while moving on a next generation wireless network. In addition, in smart factories (SFs), communication is required between factory floor and manufacturing zone, as well as connectivity towards office IT, or remote production facilities that are connected via wide area network or internet. For this purpose, interworking between heterogeneous networks is important, but there has been little research on global mobility support. Therefore, this paper proposes Proxy‐LMA technology, a mobile IP‐based global internetworking system, to improve global mobility and interoperability in the SFs network environment. The purpose of the proposed Proxy‐LMA system is to support global mobility by using mobility management protocols such as PMIPv6 and MIPv6 in heterogeneous network environment. As a result of the performance evaluation, Proxy‐LMA system is more efficient than other methods in terms of signaling cost and response delay in heterogeneous network environment. Software‐based networking in SFs enables them to easily adapt the communication network to changing requirements. Similar to cloud‐based systems, such SFs could be seen as production clusters that could be rented and configured as needed. The SF network uses software‐defined networking combined with network functions virtualization, to achieve the required flexibility. Despite the fact that the technology is nowadays not yet ready for deployment in today's manufacturing networks, a novel network architecture for SFs based on software‐defined networking and network virtualization is here proposed, to support smart services, especially for Industrie 4.0.     

An efficient pipelined architecture for real-valued Fast Fourier Transform

Real-valued Fast Fourier Transform (FFT) plays an important role in today’s digital world because of the fact that most of the signals contain real values. The FFT computation of real signals using conventional techniques requires more hardware space with high power consumption, which is the most important task for a researcher while designing VLSI architectures. This can be eradicated by clearly analysing the symmetric property of the real-valued signals. In this paper, we have adopted the symmetric property and designed an efficient pipelined architecture for 16-point DIF FFT. The pipeline scheme reduce the processing time at the cost of some registers and in order to contribute efficiently for power reduction we have modified the complex multiplier with reduced internal real multipliers which are in turn replaced by an modified canonic signed digit multiplier (CSDM) with resource-sharing technique. The complete module is synthesised and simulated using Xilinx ISE 14.1 with the target device is Virtex-5 xc5vlx110T. The experimental results verify that our implemented design is more efficient in terms of speed, area and power when comparing with similar works.     

A novel architecture of a tunable bandpass BAW-filter for a WCDMA transceiver

This paper presents an integrated tunable filter using Bulk Acoustic Wave (BAW) resonators, designed and fabricated in a 0.25 μm BiCMOS process. This filter is intended to be used in a zero-IF W-CDMA receiver between the LNA and the mixer. BAWs resonators turn out to be very attractive and competitive components thanks to their high Q-factor at high frequencies. Moreover, BAW technology, unlike Surface Acoustic Wave (SAW) technology, is compatible with Silicon process technology and allows a considerable reduction of the circuit area. However, because of its stacked structure and the thin thickness of materials to deposit, such devices are sensitive to process. They also suffer from temperature dispersions. The presented filter offers a reduced sensitivity to process and temperature variations thanks to its tunability. It allows correcting thermal and process dispersions on the piezoelectric layer of the BAW devices. The tuning is achieved through additional passive components (Q-enhanced inductance and varicaps). Simulations exhibit a tuning range of 1.4% for a 2.4 mA current consumption at 2 GHz. Good in-band linearity and noise performances have also been simulated. Stephane Razafimandimby was born in Lehon, France, in 1979. He received the engineering degree in electronics from the Institut Supérieur d'Electronique du Nord (ISEN), Lille, France, in 2003. Since 2003, he has been working toward the Ph.D. degree with STMicroelectronics, Crolles, France in collaboration with the Institut d'électronique, de Microélectronique et de Nanotechnologies (IEMN)/ISEN, Lille, France. His actual work and main research interests include RF integrated circuits and notably the feasability of integrating MEMS for mobile devices. Cyrille Tilhac was born in Tulle, France, in 1979. He received the master degree in radio-frequency and microwave communications from the Faculté des Sciences et Techniques de Limoges, France, in 2003. Since 2003, he has been working toward the Ph.D. degree with STMicroelectronics, Crolles, France in collaboration with the XLIM research laboratory, MINACOM department, Limoges, France. His actual work and main research interests include RF integrated circuits and particularly the integration of bulk acoustic wave resonators into RF devices. Andreas Kaiser (S'84, M'87) received the engineering diploma from the Institut Supérieur d'Electronique du Nord (ISEN), Lille, France, in 1984. In 1990 he received the PhD degree and in 1998 the HDR degree, both from the University of Lille. In 1990 he joined the Centre National de la Recherche Scientifique (CNRS) where he is responsible for the analog/RF IC design group at the Institut d'Electronique, de Microelectronique et de Nanotechnologies (IEMN) in Villeneuve-d'Ascq. He is also a Professor at ISEN. He published numerous papers on continuous and discrete time analog circuits, data-converters, RF-MEMS and analogue design automation. Prof. Kaiser served as Programme Chairman of the European Solid State Circuits Conference in 1995 and 2005 respectively. Andreia Cathelin was born in Bucarest, Romania. She started her electronic studies at the Polytechnic Institute of Bucarest, Romania and graduated from the Institut Supérieur d'Electronique du Nord (ISEN), Lille, France in 1994. From 1994 till 1998, she prepared a Ph. D. thesis with IEMN/ISEN, Lille, France and MS2 Company, Roubaix, France on a fully-integrated BiCMOS low power—low voltage FM/RDS receiver. From 1997 till 1998, she was with Info Technologies, Gradignan, France, working on analog and RF communications design. Since 1998, she is with STMicroelectronics, Crolles, France, in the Central R&D Division. Her major fields of interest are analog filtering, RF systems for mobile communication solutions, as well as MEMS devices co-integration. Didier Belot received the “D.U.T Electronique” degree from the “Institut Universitaire de Technologie” of Grenoble, Grenoble France in 1982, and the M.S. degree from the “Ecole Nationale Superieure d'Electronique et de Radioelectricite de Grenoble”, Grenoble France in 1991. In 1983, he joined the Bipolar Device Characterization and Modelization group, Thomson Semiconductor. In 1986, he joined Thomson “Etude et Fabrication de Circuits Integres Speciaux”, where he was involved with digital CMOS design. In 1988, he was involved with the design of high speed ECL/CML data communication ICs at STMicroelectronics. In 1996 he moves to the Radio Frequency design. Presently he manages a design group involved with the development of circuits for Mobile Phones and Local Network standards in Central Research and Development, STMicroelectronics, Crolles, France.     

MaGMA: mobility and group management architecture for real‐time collaborative applications

We introduce MaGMA, a mobility and group management architecture, enabling real‐time collaborative group applications such as push‐to‐talk (PTT) for mobile users. MaGMA provides, for the first time, a comprehensive and scalable solution for group management, seamless mobility, and quality‐of‐service (QoS). MaGMA is a distributed IP‐based architecture consisting of an overlay server network deployed as part of the service infrastructure. MaGMA's architecture consists of a collection of mobile group managers (MGMs), which manage group membership and may also implement a multicast overlay for data delivery. The architecture is very flexible, and can co‐exist with current as well as emerging wireless network technologies. We see such services as essential components in beyond‐3G (B3G) networks. We propose two group management approaches in the context of MaGMA. We devise protocols for both approaches, evaluate both solutions using simulations, and validate the results through mathematical analysis. Finally, we present a proof‐of‐concept prototype implementation. Copyright © 2005 John Wiley & Sons, Ltd.     

An efficient and flexible architecture for high-density gate arrays

The authors describe an efficient and flexible HDGA (high-density gate array) architecture (or sea of transistors) with cells containing three common-gate wide and small transistors on which both logic and memory functions can be relatively densely mapped. The use of titanium-silicide straps for local interconnect (as an alternative to the third metal layer) is evaluated through different designs. The design and performance of an experimental chip in 0.8-μm CMOS technology are discussed. In a comparison of many different standard-cell and common-gate HDGA designs, the HDGA implementations showed equal performance at comparable or even smaller chip areas     

An efficient architecture for Bandwidth Brokers in DiffServ networks

In this article we examine the architecture of an entity used for automatic management and provisioning of resources for DiffServ networks. We examine the existing literature and implementations in this area, focusing on the design choices made, and we propose an architecture for the design of Bandwidth Brokers that combines an adaptive admission control algorithm for increased utilization of network resources and a mechanism for reducing the complexity overhead that intends to be both simple and effective. Specifically, we present a novel architecture for the admission control module that aims at achieving a satisfactory balance between maximizing the resource utilization for the network provider and minimizing the overhead of the module. We complement our theoretical discussion with extensive experimental simulations for the proposed Bandwidth Broker components and analysis of the results. The simulations study the possible configurations of the proposed algorithm and also compare it with alternative admission control policies. Copyright © 2007 John Wiley & Sons, Ltd.     

AVS插值算法的一种高效的硬件结构设计与实现

提出了AVS解码系统中帧间运动补偿插值算法的一种面向FPGA/ASIC的硬件结构设计.阐述了插值过程的各功能单元的结构,给出了仿真结果及硬件规模.结果表明本文提出的结构设计支持720×576,4:2:0,30FPS的视频在54MHz最低工作频率下的实时解码,是一种适合于集成的高效并行VLSI结构设计.