A virtual metrology system for semiconductor manufacturing

Nowadays, the semiconductor manufacturing becomes very complex, consisting of hundreds of individual processes. If a faulty wafer is produced in an early stage but detected at the last moment, unnecessary resource consumption is unavoidable. Measuring every wafer’s quality after each process can save resources, but it is unrealistic and impractical because additional measuring processes put in between each pair of contiguous processes significantly increase the total production time. Metrology, as is employed for product quality monitoring tool today, covers only a small fraction of sampled wafers. Virtual metrology (VM), on the other hand, enables to predict every wafer’s metrology measurements based on production equipment data and preceding metrology results. A well established VM system, therefore, can help improve product quality and reduce production cost and cycle time. In this paper, we develop a VM system for an etching process in semiconductor manufacturing based on various data mining techniques. The experimental results show that our VM system can not only predict the metrology measurement accurately, but also detect possible faulty wafers with a reasonable confidence.     

Feature extraction for novelty detection as applied to fault detection in machinery

Novelty detection is a pattern recognition technique used when there is one well characterized normal state and the abnormal (or novel) states are poorly described because of lack of data. Data deficiency of these states may arise due to cost and difficulty in measuring them - e.g. failed equipment states in equipment health monitoring. Normal pattern recognition techniques have a wide array of methods for reducing the number of features initially employed to characterize classes. These techniques are of limited use in novelty detection primarily because they are focused on representing the data accurately in a subspace rather than on finding a subspace where the classes can easily be discriminated, or they are optimized to distinguish between all classes rather than on focusing on distinguishing solely between normal and abnormal classes. The proposed methodology will enable feature extraction in unbalanced classification problems where the well-sampled normal data is expected to be orbited by the under-sampled fault data. The technique will be demonstrated to work well with artificial and actual machinery health data.     

Kernel PCA for novelty detection

Kernel principal component analysis (kernel PCA) is a non-linear extension of PCA. This study introduces and investigates the use of kernel PCA for novelty detection. Training data are mapped into an infinite-dimensional feature space. In this space, kernel PCA extracts the principal components of the data distribution. The squared distance to the corresponding principal subspace is the measure for novelty. This new method demonstrated a competitive performance on two-dimensional synthetic distributions and on two real-world data sets: handwritten digits and breast-cancer cytology.     

Capacity planning with capability for multiple semiconductor manufacturing fabs

A capacity planning system (CPS) that considers the capacity and capability of equipment is developed for multiple semiconductor manufacturing fabs. On the basis of pull philosophy and the assumption of infinite equipment capacity, the system determines each lot's release time, start fab, and the capability of the equipment. CPS includes three main modules—the WIP-Pulling Module (WPM), the Workload Accumulation Module (WAM) and the Wafer Release Module (WRM). WPM pulls WIP from the end of the process route to meet the master production schedule (MPS). WAM then calculates the expected equipment loading in different time buckets. If WIP cannot meet the MPS requirement, then for each lot to be released, WRM evaluates the expected loading of many fabs, based on the lot's planned start time, and then determines the lot release time, the start fab and the equipment capability, to optimize the workload balance among all fabs. Simulation results indicate the effectiveness and efficiency of this system. A CPS that combines Adjusted Release Time (ART) and Path Load performs best in terms of three performance measures. This finding shows that CPS based on the combination of ART and Path Load can efficiently balance the equipment workload among the various fabs, on various days, and across various equipment at various levels of demands.     

Heuristic approaches for master planning in semiconductor manufacturing

In this paper, we propose heuristic approaches for solving master planning problems that arise in semiconductor manufacturing networks. The considered problem consists of determining appropriate wafer quantities for several products, facilities, and time periods by taking demand fulfillment (i.e., confirmed orders and forecasts) and capacity constraints into account. In addition, fixed costs are used to reduce production partitioning. A mixed-integer programming (MIP) formulation is presented and the problem is shown to be NP-hard. As a consequence, two heuristic procedures are proposed: a product based decomposition scheme and a genetic algorithm. The performance of both heuristics is assessed using randomly generated test instances. It turns out that the decomposition scheme is able to produce high-quality solutions, while the genetic algorithm achieves results with reasonable quality in a short amount of time.     

Decomposition-based classified ant colony optimization algorithm for scheduling semiconductor wafer fabrication system

Due to its typical features, such as large-scale, multiple re-entrant flows, and hybrid machine types, the semiconductor wafer fabrication system (SWFS) is extremely difficult to schedule. In order to cope with this difficulty, the decomposition-based classified ant colony optimization (D-CACO) method is proposed and analyzed in this paper. The D-CACO method comprises decomposition procedure and classified ant colony optimization algorithm. In the decomposition procedure, a large and complicate scheduling problem is decomposed into several subproblems and these subproblems are scheduled in sequence. The classified ACO algorithm then groups all of the operations of the subproblems and schedules them according to machine type. To test the effect of the method, a set of simulations are conducted on a virtual fab simulation platform. The test results show that the proposed D-CACO algorithm works efficiently in scheduling SWFS.     

Bayesian Belief Network-based approach for diagnostics and prognostics of semiconductor manufacturing systems

Semiconductor manufacturing is a complex process in that it requires different types of equipments (also referred to as tools in semiconductor industry) with various control variables under monitoring. As the number of sensors grows, a huge amount of data are collected from the production; and yet, the relations among these control variables and their effects on finished wafer are to be fully understood for both equipment monitoring and quality assurance. Meanwhile, as the wafer goes through multiple periods with different recipes, failure that occurs during the process can both cause tremendous loss to manufacturer and compromise product quality. Therefore, occurred failure should be detected as soon as possible, and root cause need to be identified so that corrections can be made in time to avoid further loss. In this paper, we propose to apply Bayesian Belief Network (BBN) to investigate the causal relationship among process variables on the tool and evaluate their influence on wafer quality. By building BBN models at different periods of the process, the causal relation between control parameters, and their influence on wafer can be both qualitatively indicated by the network structure and quantitatively measured by the conditional probabilities in the model. In addition, with the BBN probability propagation, one can diagnose root causes when bad wafer is produced; or predict the wafer quality when abnormal is observed during the process. Our tests on a Chemical Vapor Deposition (CVD) tool show that the BBN model achieves high classification rate for wafer quality, and accurately identifies problematic sensors when bad wafer is found.     

Evaluating investment-return-based design for AMHS in semiconductor manufacturing system

An effective automated material handling system (AMHS) design improves production performance. Investment return is a primary concern for high technology companies when purchasing production equipment. This study demonstrates that when profit gained from investing in non-production equipment investment can be estimated, investment return can be evaluated and used as an investment index for non-production equipment. An effective approach based on Little’s law for AMHS design is proposed. This approach quantifies system improvement resulting from a specific AMHS design. Then, an activity and theory of constraints based (ABC/TOC) costing model is used to capitalize the improvement. Finally, the investment-return time length for that specific design can be evaluated. An investor can easily decide among several designs when using the proposed approach.     

半导体芯片电路线宽显微测量精度分析

在显微图像的尺寸测量中．由于各种因素的影响．测量结果不可避免地存在着误差．为了充分认识并进而减小这些误差，提高测量精度．文章对标准件标定、显微光学系统的景深、对焦、光照亮度以及温度等影响测量结果的误差源作了细致的研究，给出了半导体芯片电路线宽显微测量结果及精度分析。     

Multiple-objective scheduling and real-time dispatching for the semiconductor manufacturing system

Implementing efficient scheduling and dispatching policies is a critical means to gain competitiveness for modern semiconductor manufacturing systems. In contemporary global market, a successful semiconductor manufacturer has to excel in multiple performance indices, consequently qualified scheduling approaches should provide efficient and holistic management of wafer products, information and manufacturing resources and make adaptive decisions based on real-time processing status to reach an overall optimized system performance. To cope with this challenge, a timed extended object-oriented Petri nets (EOPNs) based multiple-objective scheduling and real-time dispatching approach is proposed in this paper. Four performance objectives pursued by semiconductor manufacturers are integrated into a priority-ranking algorithm that serves as the initial scheduling guidance, and then all wafer lots will be dynamically dispatched by the hybrid real-time dispatching control system. A set of simulation experiments validate the proposed multiple-objective scheduling and real-time dispatching algorithm may achieve satisfactory performances.     

A new strategy for defect inspection by the virtual inspection in semiconductor wafer fabrication

The defect of process equipments is a major factor that impairs the yields in the mass production of semiconductor wafer fabrication and it is a main supervision means to use high-resolution defect inspection tools to detect and monitor the defect damage. Due to the high investment costs of these inspection tools and the resulting decrease in the throughput, how to improve the sampling rate is an important issue for the associated inspection strategy. This paper proposes a new concept and implementation of virtual inspection (VI) to enhance the detection and monitoring of defect in semiconductor production process. The underlying theory of the VI concept is that the state variables identifications (SVIDs) of process equipments can reflect the process quality effectively and loyally. The approach of VI is to combine the application of the fault detection and classification (FDC), and the defect library and the re-engineering of inspection procedure to reach the full-scope of strategic objective. VI enables the defect monitoring to enter a new era by promoting the monitoring level of defect inspection from the previous lot-sampling basis to the wafer-sampling level, and hence upgrades the sampling strategy from random-sampling to full and right-sampling. In this study, various typical defect cases are utilized to illustrate how to create VI models and verify the reliability of the proposed approach. Furthermore, a feasible architecture of the VI implementation for mass production in semiconductor factory is presented in the paper.     

A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing

Wafer fabrication for semiconductor manufacturing consists of multiple layers, in which the displacements (i.e., overlay errors) between layers should be reduced to enhance the yield. Although it can reduce variance between layers by fixing the exposure machine (i.e. steeper or scanner), it is not practical to expose the wafer on the same machine from layer to layer for the lengthy fabrication process in real setting. Thus, there is a critical need to determine the similarity machine subgroups, in which appreciate backups for unexpected machine down can be also prioritized. This study aims to develop a novel methodology to fill this gap based on the proposed similarity measurement of systematic overlay errors and residuals. The proposed methodology was validated via empirical study in a wafer fab and the results showed practical viability of this approach. Received: May 2005 / Accepted: December 2005     

Automatic defect classification for semiconductor manufacturing

Visual defect inspection and classification are important parts of most manufacturing processes in the semiconductor and electronics industries. Defect classification provides relevant information to correct process problems, thereby enhancing the yield and quality of the product. This paper describes an automated defect classification (ADC) system that classifies defects on semiconductor chips at various manufacturing steps. The ADC system uses a golden template method for defect re-detection, and measures several features of the defect, such as size, shape, location and color. A rule-based system classifies the defects into pre-defined categories that are learnt from training samples. The system has been deployed in the IBM Burlington 16 M DRAM manufacturing line for more than a year. The system has examined over 100 000 defects, and has met the design criteria of over 80% classification rate and 80% classification accuracy. Issues involving system design tradeoff, implementation, performance, and deployment are closely examined.     

A generalized Petri net modeling approach for the control of re-entrant flow semiconductor wafer fabrication

Re-entrant flow manufacturing lines, such as occur in semiconductor wafer fabrication, are characterized by a product routing that consists of multiple visits to a workstation or group of workstations during the manufacturing process. In this paper, a modeling approach is based on the use of generalized Petri nets for a re-entrant flow manufacturing line is presented. Specifically, three Petri net models representing a re-entrant flow line with three work centers and six machines are modeled. How these models may be used to represent a variety of queuing disciplines and work release policies is discussed.     

Machine-vision-based identification for wafer tracking in solar cell manufacturing

Solar power is getting popular as an alternative of electricity energy. Multicrystalline solar cells dominate the current market share because of lower material and manufacturing costs. In solar cell manufacturing, a silicon ingot is sliced into thin wafers and then the wafers are further processed into solar cells. Conventional automatic identification systems such as bar codes, magnetic strips, OCR and RFID need a contacted identity on the object surface. They are not possible to implement for solar wafer tracking and data collection due to the thin, fragile silicon surface of a solar wafer.     

Information fusion for simulation based decision support in manufacturing

Robust and informed decisions are important for the efficient and effective operation of installed production facilities. The paper discusses Information fusion (IF) including a generic model for IF, and situations for decision-making. The paper also discusses current and future use of manufacturing resource simulation for design/configuration, operational planning and scheduling, and service and maintenance of manufacturing systems. Many of these applications use IF in some way, as is explained in more detail for simulation based service and maintenance. An extension of the generic model for IF is presented which incorporates modeling and simulation, and active databases as used in a simulation based service and maintenance system at the authors’ laboratory.     

Constraint feedforward control for thermal processing of quartz photomasks in microelectronics manufacturing

A feedforward control scheme is designed to improve performance of conductive heating systems used for lithography in microelectronics processing. It minimizes the loading effects induced by the common processing condition of placement of a quartz photomask at ambient temperature on a bake plate at processing temperature. The feedforward control strategy is a model-based method using linear programming to minimize the worst-case deviation from a nominal temperature set-point during the load disturbance condition. This results in a predictive controller that performs a pre-determined heating sequence prior to the arrival of the substrate as part of the resulting feedforward/feedback strategy to eliminate the load disturbance. This procedure is based on an empirical model generated from data obtained during closed-loop operation. It is easy to design and implement for conventional thermal processing equipment. Experimental results are performed for two commercial bake plates and depict an order-of-magnitude improvement in the settling time and the integral-square temperature error between the optimal predictive controller and a feedback controller for a typical load disturbance.     

Inventory write-down prediction for semiconductor manufacturing considering inventory age,accounting principle,and product structure with real settings

The International Financial Reporting Standards (IFRS) No. 2 has been the worldwide accounting principle for the reduction of inventory to market allowance since January 1, 2005. Using make-to-stock manufacturing strategies and inventory accounting for only approximately 14% of the total costs, integrated device manufacturers have found maintaining robust records for financial statements increasingly difficult. For example, one company in the case study conducted in this study must write-down losses of 2–100% of the total inventory costs for products with inventory ages of 18 months–3 years. However, the average cycle time for producing flash memory is approximately 3 months. In other words, when the system variation and safety stock policy are considered, the company must write-down the reduction of inventory to market allowance for most of work-in-process inventory. However, little research has been done to addressing the practical management of operations according to inventory aging processes. This study develops a polynomial-time-based model to obtain significant features, including inventory ages, accounting principles, and product structures (bill of material), for the accurate prediction of inventory write-downs to reduce the impact of the carrying value fluctuation of inventory. An empirical study was conducted on a Taiwanese semiconductor manufacturer. The results show that predicting 3-month inventory write-downs of a complete flash memory production line comprising approximately 8500 product types can be conducted in less than 10 s, with the mean absolute percentage error (MAPE) less than 3.5%. Discussions regarding the sensitivity analysis and cost tornado diagrams suggest the priority of affecting factors. The results show the viability of implementing the proposed model to predict inventory write-downs in the semiconductor manufacturing industry.     

A time series representation model for accurate and fast similarity detection

Similarity search and detection is a central problem in time series data processing and management. Most approaches to this problem have been developed around the notion of dynamic time warping, whereas several dimensionality reduction techniques have been proposed to improve the efficiency of similarity searches. Due to the continuous increasing of sources of time series data and the cruciality of real-world applications that use such data, we believe there is a challenging demand for supporting similarity detection in time series in a both accurate and fast way. Our proposal is to define a concise yet feature-rich representation of time series, on which the dynamic time warping can be applied for effective and efficient similarity detection of time series. We present the Derivative time series Segment Approximation (DSA) representation model, which originally features derivative estimation, segmentation and segment approximation to provide both high sensitivity in capturing the main trends of time series and data compression. We extensively compare DSA with state-of-the-art similarity methods and dimensionality reduction techniques in clustering and classification frameworks. Experimental evidence from effectiveness and efficiency tests on various datasets shows that DSA is well-suited to support both accurate and fast similarity detection.     

A deadlock recovery strategy for unified automated material handling systems in 300 mm wafer fabrications

A key issue emerging from the unified automated material handling systems (UAMHSs) in 300 mm wafer fabrications is the system deadlock. This paper addresses the deadlock recovery strategy of unified automated material handling systems (UAMHSs) with limited buffers. A formal model for UAMHSs deadlock detection is proposed. Sufficient conditions for system deadlocks based on actual UAMHS characteristics are defined along with a novel deadlock recovery strategy. Moreover, an effective heuristic algorithm is proposed for parallel resolving UAMHS deadlocks. The performances are evaluated in simulation by monitoring indexes reflecting efficiency of the material handling system. Results of the simulation experiments show that the novel deadlock recovery strategy is superior to the benchmark strategy in reducing deadlock time and improving tools’ utilization. Furthermore, the proposed algorithm features real-time operation and large scale cases, and is suitable for practical applications.