A regular fabric design methodology for applications requiring specific layout-level design rules

Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs.In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side-channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5×slower and 2.3×bigger than a standard cell implantation, but also on average 13×faster than a FPGA.     

Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA

Programmable devices are an interesting alternative when implementing embedded systems on a low-volume scale. In particular, the affordability and the versatility of SRAM-based FPGAs make them attractive with respect to ASIC implementations. FPGAs have thus been used extensively and successfully in many fields, such as implementing cryptographic accelerators. Hardware implementations, however, must be protected against malicious attacks, e.g. those based on fault injections. Protections have been usually evaluated on ASICs, but FPGAs can be vulnerable as well. This work presents thus fault injection attacks against a secured AES architecture implemented on a SRAM-based FPGA. The errors are injected during the computation by means of voltage glitches and laser attacks. To our knowledge, this is one of the first works dealing with dynamic laser fault injections. We show that fault attacks on SRAM-based FPGAs may behave differently with respect to attacks against ASIC, and they need therefore to be addressed by specific countermeasures, that are also discussed in this paper. In addition, we discuss the different effects obtained by the two types of attacks.     

DSP system integration and prototyping with FPGAS

Field Programmable Gate Arrays (FPGAs) offer a cost-effective and flexible technology for DSP ASIC prototype development. In this article, the fast ASIC prototyping concept based on the use of multiple FPGAs is reviewed in different engineering applications. The design experiences of the proposed approach, applied to four different DSP ASIC design projects are presented. The design experiences concerning the selection of the design methodology, application architectures and prototyping technologies are analyzed with respect to efficient system integration and ASIC migration from the FPGA prototype onto first-time functional silicon. Novel prototyping techniques based on using configurable hardware modellers concerning the same objective are studied. Some future goals are outlined to develop an integrated, multipurpose DSP ASIC prototyping environment.     

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.     

FPGAs achieve superior speed and density with antifuse advancements

FPGAs based on low-resistance, low-capacitance “antifuse” programmable elements offer very high-speed performance with small, cost-effective die sizes for high-volume production applications. FPGA vendors continue to invest in this technology to push further into the performance and density/cost realm previously dominated by conventional mask programmed ASICs. These high-performance, high-density antifuse based products will further distance themselves in speed, cost, and ease-of-use from slower, more costly RAM-based FPGAs.     

Routability of Network Topologies in FPGAs

A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto a modern FPGA routing fabric. Different multiprocessor network topologies with between 8 and 64 nodes are mapped to a single large FPGA. Except for the fully-connected networks, it is observed that the difference in logic resources used and routing overhead among these topologies is insignificant for the systems tested. Fully-connected networks up to about 22 nodes are also feasible on the same FPGA although the logic and routing utilization clearly grows much faster. The conclusion is that a modern FPGA fabric is very rich in resources and capable of supporting highly interconnected topologies. For systems with a modest number of nodes implemented on current large FPGAs, it is not necessary to use the connectivity-limited topologies typically used for networks-on-chip. Rather, direct point-to-point connections between all communicating nodes can be considered.     

Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA

An Application Specific Inflexible FPGA (ASIF) is a modified form of an FPGA which is designed for a predefined set of applications that operate at mutually exclusive times. An ASIF is a compromise between FPGAs and Application Specific Integrated Circuits (ASICs). Compared to an FPGA, an ASIF has reduced flexibility and improved density while compared to an ASIC, it has larger area but improved flexibility. This work presents a new homogeneous tree-based ASIF and uses a set of 16 MCNC benchmarks for experimentation. Experimental results show that, on average, a homogeneous tree-based ASIF gives 64% area gain when compared to an equivalent tree-based FPGA. Further, the experiments are performed to explore the effect of look-up table (LUT) and arity size on a tree-based ASIF. Later, comparison between tree and mesh-based ASIF is performed and results show that tree-based ASIF is 12% smaller in terms of routing area and consumes 77% less wires than mesh-based ASIF. Finally the quality comparison between two ASIFs reveals that, on average, tree-based ASIF gives 33% area gain as compared to mesh-based ASIF.     

基于BUFGMUX与DCM的FPGA时钟电路设计

与ASIC(专用集成电路)的时钟电路相比,基于FPGA(现场可编程门阵列)的时钟电路有其自身的特点。FPGA一般提供专用时钟资源搭建时钟电路,相应的综合工具也能够自动使用这些资源,但是针对门控时钟和时钟分频电路,如果直接使用综合工具自动处理的结果,会造成较大的时钟偏差。通过合理使用DCM(数字时钟管理单元)和BUFG-MUX(全局时钟选择缓冲器)等FPGA的特殊资源,手动搭建时钟电路,可以尽可能地减少时钟偏差对电路时序的影响。     

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.     

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

The latest SRAM-based FPGA devices are making the development of low-cost, high-performance, re-configurable systems feasible, paving the way for innovative architectures suitable for mission- or safety-critical applications, such as those dominating the space or avionic fields. Unfortunately, SRAM-based FPGAs are extremely sensitive to Single Event Upsets (SEUs) induced by radiation. SEUs may alter the logic value stored in the memory elements the FPGAs embed. A large part of the FPGA memory elements is dedicated to the configuration memory, whose content dictates how the resources inside the FPGA have to be used to implement any given user circuit, SEUs affecting configuration memory cells can be extremely critics. Facing the effects of SEUs through radiation-hardened FPGAs is not cost-effective. Therefore, various fault-tolerant design techniques have been devised for developing dependable solutions, starting from Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs. These techniques present advantages and disadvantages that must be evaluated carefully to exploit them successfully. In this paper we mainly adopted an empirical analysis approach. We evaluated the reliability of a multiplier, a digital FIR filter, and an 8051 microprocessor implemented in SRAM-based FPGA’s, by means of extensive fault-injection experiments, assessing the capability provided by different design techniques of tolerating SEUs within the FPGA configuration memory. Experimental results demonstrate that by combining architecture-level solutions (based on redundancy) with layout-level solutions (based on reliability-oriented place and route) designers may implement reliable re-configurable systems choosing the best solution that minimizes the penalty in terms of area and speed degradation.     

The flexibility of configurable computing

There has been growing recent interest in configurable computing, which can be viewed as a hybrid between ASICs and programmable processors. Configurable computing machines are implemented with programmable logic: flexible hardware that can be structured to fit the natural organization and data flow of a computation. The enabling device for configurable computing is the field-programmable array (FPGA). For applications characterized by deeply pipelined, highly parallel, and integer arithmetic processing, configurable computing machines can outperform alternative solutions by up to an order of magnitude. The combination in a single device of dedicated hardware and rapid, submillisecond-scale reprogrammability constitutes an exciting and promising development whose implications are only just beginning to be exploited. We begin with a brief tutorial on FPGAs that describes the most common FPGA architectures and how these architectures are used to support computation, memory access, and data flow. We then present FPGAs as computing machines and focus on devices that are reconfigured during run time. Ongoing research involving FPGAs and future directions are also discussed     

Configurable logic for digital communications: some signalprocessing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies     

FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures

Physically Unclonable Functions (PUFs) are a promising technology and have been proposed as central building blocks in many cryptographic protocols and security architectures. Among other uses, PUFs enable chip identifier/authentication, secret key generation/storage, seed for a random number generator and Intellectual Property (IP) protection. Field Programmable Gate Arrays (FPGAs) are re-configurable hardware systems which have emerged as an interesting trade-off between the versatility of standard microprocessors and the efficiency of Application Specific Integrated Circuits (ASICs). In FPGA devices, PUFs may be instantiated directly from FPGA fabric components in order to exploit the propagation delay differences of signals caused by manufacturing process variations. PUF technology can protect the individual FPGA IP cores with less overhead. In this article, we first provide an extensive survey on the current state-of-the-art of FPGA based PUFs. Then, we provide a detailed performance evaluation result for several FPGA based PUF designs and their comparisons. Subsequently, we briefly report on some of the known attacks on FPGA based PUFs and the corresponding countermeasures. Finally, we conclude with a brief overview of the FPGA based PUF application scenarios and future research directions.     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

NEW APPROACH TO EMULATE SEU FAULTS ON SRAM BASED FPGAS简

Field Programmable Gate Arrays （FPGAs） offer high capability in implementing of com- plex systems, and currently are an attractive solution for space system electronics. However, FPGAs are susceptible to radiation induced Single-Event Upsets （SEUs）. To insure reliable operation of FPGA based systems in a harsh radiation environment, various SEU mitigation techniques have been provided In this paper we propose a system based on dynamic partial reconfiguration capability of the modern devices to evaluate the SEU fault effect in FPGA. The proposed approach combines the fault injection controller with the host FPGA, and therefore the hardware complexity is minimized. All of the SEU injection and evaluation requirements are performed by a soft-core which realized inside the host FPGA Experimental results on some standard benchmark circuits reveal that the proposed system is able to speed up the fault injection campaign 50 times in compared to conventional method.     

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures

Recently, FPGAs (field programmable gate arrays) technology have made significant advances in both speed and capacity. Millions of logic gates are now available for reconfiguration programming. To fully exploit the potential of so many programmable devices, powerful design methodology must be developed. In this paper, we propose a novel systematic computer-aided design methodology that can efficiently implement deeply nested do-loop algorithms on a FPGA. Specifically, our design methodology maps the loop dependence graph onto a linear array of locally connected processing elements to exploit parallelism. Due to the regular structure of this linear array of processors, it can be easily implemented on a FPGA. While this method is based on conventional systolic array design methodology, our proposed approach exhibits two distinct features that contribute to its superior performance: 1) We developed a novel multiple-order dependence graph representation that is able to efficiently represent distinct, yet correct algorithm execution orders. 2) We developed new FPGA-specific architectural constraints during the mapping process. As such, FPGA implementations based on our approach will utilize much fewer lookup tables while achieving superior performance.     

FPGAs as reconfigurable processing elements

In most applications, FPGAs are used to implement “glue logic”, providing the advantages of high integration levels without the expense and risk of custom ASIC development. However, as SRAM-based FPGA devices have increased in capability, their use as in-system-configurable computing elements is receiving considerable attention. Indeed, reconfigurable FPGA technology holds the potential for reshaping the future of computing by providing the capability to dynamically alter a computer's hardware resources to optimally service immediate computational needs. Computing circuits built from SRAM-based FPGAs can meet the true goal of parallel processing-executing algorithms in circuitry with the inherent parallelism of hardware, while avoiding the instruction fetch and load/store bottlenecks of traditional von Neumann architectures. There are many computationally-intensive algorithms that can benefit from being partially or wholly implemented in hardware. Typically, these algorithms are too specialized to justify the expense of manufacturing custom IC devices     

An FPGA-based performance evaluation of the AES block ciphercandidate algorithm finalists

The technical analysis used in determining which of the potential Advanced Encryption Standard candidates was selected as the Advanced Encryption Algorithm includes efficiency testing of both hardware and software implementations of candidate algorithms. Reprogrammable devices such as field-programmable gate arrays (FPGAs) are highly attractive options for hardware implementations of encryption algorithms, as they provide cryptographic algorithm agility, physical security, and potentially much higher performance than software solutions. This contribution investigates the significance of FPGA implementations of the Advanced Encryption Standard candidate algorithms. Multiple architectural implementation options are explored for each algorithm. A strong focus is placed on high-throughput implementations, which are required to support security for current and future high bandwidth applications. Finally, the implementations of each algorithm will be compared in an effort to determine the most suitable candidate for hardware implementation within commercially available FPGAs     

基于ASIC技术的电子防盗系统及其实现

提出了一种将专用集成电路应用于电子防盗系统设计的新方法。介绍了系统组成和工作流程,给出了ＦＰＧＡ验证结果。该系统利用ＡＳＩＣ保密性能好的特点,工作时误报率低。