A dynamic electro-thermal model for the IGBT

A physics-based dynamic electrothermal model is developed for the IGBT by coupling a temperature-dependent IGBT electrical model with dynamic thermal models for the IGBT silicon chip, packages, and heatsinks. The temperature-dependent IGBT electrical model describes the instantaneous electrical behavior in terms of the instantaneous temperature of the IGBT silicon chip surface. The instantaneous power dissipated in the IGBT is calculated using the electrical model and determines the instantaneous rate that heat is applied to the surface of the silicon chip thermal model. The thermal models determine the evolution of the temperature distribution within the thermal network and thus determine the instantaneous value of the silicon chip surface temperature used by the electrical model. The IGBT electrothermal model is implemented in the Saber circuit simulator and is connected to external circuits in the same way as the previously presented Saber IGBT model, except that it has an additional thermal terminal that is connected to the thermal network component models for the silicon chip, package, and heatsink. The IGBT dynamic electrothermal model and the thermal network component models are verified for the range of temperature and power dissipation levels (heating rates) that are important for power electronic systems     

EE-BESD: molecular FET modeling for efficient and effective nanocomputing design

Molecular transistor is a good candidate as substitute of CMOS device due to small size, expected good performance and suitability to be included in high density-circuits. To date a lot of effort has been carried out to understand the conduction properties in molecular devices. However, minor effort has been devoted to reduce their computational complexity to obtain a compact molecular model. First-principle based methods frequently used are highly computational demanding for a single device, thus they are not suitable for complex circuit design. In this paper we present an accurate and at the same time computationally efficient method (named Efficient and Effective model based on Broadening level, Evaluation of peaks, SCF and discrete levels, ee-besd) to calculate the electron transport characteristics of molecular transistors in presence of applied bias and gate voltages. The results obtained show a remarkable improvement in terms of computational time with respect to existing approaches, while maintaining a very good accuracy. Finally, the ee-besd model has been embedded in a circuit level simulator in order to show its functionalities and, particularly, its computational cost. This is shown to be affordable even for circuits based on a high number of devices.     

A companion macromodelling approach for the transient analysis of MOS large-scale integrated circuits

Purpose of this work is to present a new macromodelling approach for the simulation at the device level of large MOS integrated circuits, requiring only marginal modifications to be implemented in the widely used circuit simulator SPICE. This method results in a substantial saving in computing time and guarantees the same accuracy of SPICE. A prototype simulator based on this method has been developed and used to analyse several significant circuits. In addition, since the method is particularly suitable to be implemented in parallel computers, some results obtained with the CRAY-YMP/432 computer are provided.     

Analytical model of hot carrier degradation in uniaxial strained triple-gate FinFET for circuit simulation

The triple-gate (TG) SOI FinFET has well suppressed short-channel effects compared to planar MOSFET due to increased gate voltage controllability. However, the hot carrier injection (HCI) is a serious reliability issue for nanoscale FinFET and this should be taken care for reliable circuit design. The introduction of uniaxial strain in the channel of FinFET to enhance the performance further limits the reliable design of VLSI circuits. Hence, there is a great need to capture these device-level variations in circuits through physics-based models. In this paper, one such analytical model of hot carrier (HC) degradation in uniaxial strained TG FinFET based on reaction–diffusion mechanism is developed, considering various geometrical aspects of the device, for the first time. The developed model is validated using experimentally calibrated Sentaurus TCAD simulation results. The results show that the strain in the channel worsens the degradation of threshold voltage due to HCI. The developed model is integrated in Cadence circuit simulator, and the impact of HC degradation in strained TG FinFET-based CMOS NAND logic circuit is analyzed.     

新型半导体集成磁敏传感器的研究

本文论述了一种新颖的集成磁敏传感器，它是以互补三漏ＭＯＳ晶体管为磁敏器件，采用半导体集成电路技术，将放大电路，偏置电路与磁敏集成在同一芯片上。该传感器具有灵敏度高，功耗低和体积小等特点。     

An improved macromodel for operational amplifiers

The proposed macromodel in this paper precisely simulates almost all performance characteristics of integrated circuit operational amplifiers. It is shown by an example that the model bears very strong resemblance to actual circuits, A detailed comparison with other existing models demonstrates the great advantages of the proposed model. the simplicity and accuracy together with the employment of the most popular circuit simulator SPICE2 enable design engineers to use the macromodel on CAE workstations for all general purpose applications.     

基于Ansys的超声波电机驱动单元的热仿真

本文根据RTWUSM驱动电路的特点,拟用MCM技术对部分电路进行集成设计,应用Ansys对该驱动集成单元在不同对流情况下进行热仿真,模拟得到集成单元中的温度分布及散热状况,分析结果表明在空气强制对流情况下比空气自然对流时电机驱动控制装置内的芯片最高结温要低,散热状况较好,从而为电机驱动控制电路的集成设计提供理论依据.     

Electrothermal Monte Carlo simulation of submicron wurtzite GaN/AlGaN HEMTs

We present results from the simulation of the electrothermal behaviour of submicron wurtzite GaN/AlGaN High Electron Mobility Transistors (HEMTs). The simulator uses an iterative procedure which couples a Monte Carlo simulation with a fast Fourier series solution of the Heat Diffusion Equation (HDE). The results demonstrate the dependence of the extent of the thermal droop observed in the I_ds-V_ds characteristics and the device peak temperature on the device bias. The paper also investigates the effect of the inclusion of thermal self-consistency on the device microscopic properties and studies the dependence of the device electrothermal characteristics on the type of substrate material used.     

Fast 3D thermal simulation of power module packaging

This paper presents a thermal model that uses a Fourier series solution to the heat equation to carry out transient 3D thermal simulation of power device packaging. The development and implementation of this physics‐based method is described. The method is demonstrated on a stacked 3D multichip module. The required aspects of 3D heat conduction are captured successfully by the model. Compared with previous thermal models presented in literature, it is fast, accurate and can be easily integrated with an inverter circuit simulator to model realistic converter load cycles. Copyright © 2012 John Wiley & Sons, Ltd.     

An Undergraduate Integrated Circuit Fabrication Laboratory

Over the last few years an integrated circuit fabrication laboratory intended primarily for use by undergraduates has been developed within the School of Electrical Engineering at Purdue University. Operating under the principle that integrated circuit design and laboratory practice are inseparable, the main objective was to allow the undergraduate student to acquire a working knowledge of how transistors, thin- and thick-film circuits, MOS field-effect transistors, and integrated circuits are fabricated. The emphasis is on how to fabricate the device in the laboratory and then to evaluate the device both electrically and metallurgically. This paper describes in detail how a device laboratory was organized for undergraduates with a minimal background in experimental technique.     

A macromodel of sample-and-hold circuits

A concise macromodel of sample-and-hold circuits for the simulator SPICE is proposed. This generalized model is independent from actual technical realizations and is based upon compromises regarding the representation of exact circuit structures in the model. Different types of feedback and hold capacitor connections corresponding to the standard external circuit application are accounted for in the model internally. The macromodel allows one to simulate arbitrary user circuits with respect to the behaviour in both the time and frequency domains including error parameters and the temperature dependence of several parameters. Model parameters are extracted for the integrated sample-and-hold circuit AD585 from Analog Devices as an example. Simulation results and selected diagrams are compared with the manufacturer's data. © 1997 by John Wiley & Sons, Ltd.     

Harmonic balance method applied to the numerical electrical physical modelling of two-terminal,non-linear microwave circuits in the frequency domain

A numerical frequence-domain modelling of two-terminal, non-linear microwave circuits is presented. It basically relies on a process allowing the solution of the frequency-domain curcuit harmonic balance equations while accounting for the semiconductor device by means of an accurate numerical macroscopic physical model. In its present state of development, the model allows the study of a single two-terminal device circuit operating in harmonic mode. Its capabilites are illustrated by means of the results of a study devoted to the optimization of the load curcuit configuration of a millimetre-wave avalanche diode frequency multiplier. The influence of the output load impedance level on the circuit output RF performance has been investigated for different input power levels in direct frequency multiplication mode and in the presence of additional circuit tunings at low harmonic rank idler frequencies.     

Functional relaxations and spectral techniques in Computer-Aided circuit analysis

Analysis of transients in integrated circuits is performed with the use of highly specialized computer programs. The transient responses are computed using time-marching integration methods and require a substantial amount of computer time. A new method based on spectral analysis and waveform relaxation is proposed. The method results in a substantial saving in computing time without compromising the accuracy. A basic algorithm utilizing the spectral technique in a relaxation framework is described. A prototype simulator based on the algorithm was developed and used to simulate certain types of CMOS circuits. The results showed a significant time savings in comparison with the widely used circuit simulator ‘SPICE’. Example circuits and relevant results are provided.     

The Parametric Yield Enhancement of Integrated Circuits

Even where a satisfactory circuit design has been achieved, it is often the case that, owing to variations in the manufacturing process, some of the samples of a mass-produced circuit will violate the specifications on performance so that the manufacturing yield is less than 100%. Such an undesirable effect can, however, be minimized or even eliminated by redesign of the circuit to the extent of changing parameter values while retaining the original circuit topology. For discrete component circuits algorithms are available to achieve such redesign. the special characteristics of integrated circuits, however, are such that these methods are unsuitable as they stand. Two new algorithms for handling the yield enhancement of integrated circuits are described and their successful application is illustrated in the context of two-stage CMOS op amps.     

A general method for small-signal circuit analysis considering thermal effects

It is well known that the behaviour of integrated circuits is strongly affected by thermal feedback. A general method for evaluating, by linear analysis, the complete circuit performance is described that considers these effects. The procedure can easily be implemented using only well known computer programs for the circuit analysis. Simple models for a number of devices (diodes, transistors and f.e.t.s) used in integrated circuits are given. Examples, using the circuit-analysis program ECAP, are shown.     

Finite element power diode model optimized through experiment‐based parameter extraction

This paper presents a finite element physics‐based power diode model with parameters established through an extraction procedure validated experimentally. The model core is a numerical module that solves the ambipolar diffusion equation through a variational formulation followed by an approximate solution with the finite element method. Other zones of the device are modeled with classical methods in an analytical module. This hybrid approach enables accurate modeling and simulation of power bipolar semiconductor devices, using standard SPICE circuit simulators, with low execution times. As physics‐based models need a significant number of parameters, an automatic parameter extraction method has been developed. The procedure, based on an optimization algorithm (simulated annealing), enables an efficient extraction of parameters using some simple device waveform measurements. Implementation details of power diode model, in IsSpice simulator, are presented. Experimental validation is performed. Results prove the usefulness of the proposed methodology for efficient design of power circuits through simulation. Copyright © 2008 John Wiley & Sons, Ltd.     

A tabular source approach to modelling and simulating device and circuit noise in the time domain

Simulation of device and circuit noise at low frequencies is often carried out as part of a small‐signal ac analysis. Moreover, circuit simulators with rf analysis capabilities usually specify circuit performance in terms of S parameters and model high‐frequency noise in terms of noise waves and correlation matrices. It is also unusual to find circuit simulators that extend noise simulation to the time domain. This is particularly true for software packages developed from SPICE 2g6 or 3f5. This paper introduces a simple tabular noise source technique, which adds time‐domain noise to semiconductor device models and integrated circuit macromodels. The proposed technique is suitable for use with any general purpose circuit simulator. To demonstrate the power of the suggested approach the text describes time‐domain noise extensions to the SPICE diode, BJT, JFET, MOSFET and MESFET models. These noise extensions have been implemented and tested with the ‘Quite universal circuit simulator’ (Qucs). Copyright © 2011 John Wiley & Sons, Ltd.     

Limitations and complexity of digital hardware simulators used for large-scale analogue circuit and system dynamics

Large-scale electronic circuits and systems are considered with increasing complexity measured in terms of the number of circuit or system elements. the dynamics will be calculated by a digital prototype hardware simulator exploiting parallelism, pipelining and look-up table techniques to realize minimum solution time. Our ‘canonical’ conceptual prototype digital simulator (PDS) is given and its parts are analysed in detail, including a minimal memory realization of a multivariable non-linear mapping (look-up table). It is shown that if the increase of the complexity of the simulator does not exceed the increase of the complexity of the circuit or system to be simulated, then the simulation complexity (measured in terms of the accumulated time of basic calculation steps) will not decrease, but instead will increase. Hence there is an inherent limitation in the digital simulation of analogue operators. This result suggests at the same time that the digital method of data and signal processing has some inherent limitations, a striking example of overcoming it being the neural circuit. the speeding up of the digital hardware due to the scaling down of feature sizes in integrated circuits and the reduction of the time step due to the increase in system size are also taken into account.