NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors

This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell-area overhead. New capacitor-on-metal/via-stacked-plug process technologies permit a nonvolatile SRAM (NV-SRAM) cell to consist of a six-transistor ASIC SRAM cell and two backup ferroelectric capacitors stacked over the SRAM portion. READ and WRITE operations in this NV-SRAM cell are very similar to those of a standard SRAM, and this NV-SRAM shares almost all the circuit properties of a standard SRAM. Because each memory cell can perform STORE and RECALL individually, both can execute massive-parallel operations. A V_dd/2 plate-line architecture makes READ/WRITE fatigue negligible. A 512-byte test chip was successfully fabricated to show compatibility with ASIC technologies     

A 256K CMOS SRAM with variable impedance data-line loads

A 256K (32K/spl times/8) CMOS SRAM utilizing variable impedance loads and a pulsed word-line (PWL) technique is described. In the WRITE cycle, the variable impedance loads of the data lines enter a high impedance state and reduce the operating power. During the READ cycle, the PWL technique is used to achieve high-speed operation and low power dissipation. The internal clocks generated by the address transition detectors activate word-line and sense amplifiers for READ operation and disable them after the data are sent to D/SUB out/ buffers. This PWL technique eliminates the precharge time of 20 ns, which corresponds to 30% of the access time. The RAM offers 45-ns address access time and 40-mW operating power in the WRITE cycle of 1 MHz.     

基于低摆幅策略的低功耗多端口寄存器文件设计

本文通过使用低摆幅策略和修改的与非型地址译码器设计了一种低功耗的寄存器文件。该低摆幅策略基于反馈机制并利用动态逻辑减少主动反馈引入的功耗。低摆幅策略分为读写两部分。在低摆幅写策略中,设计了一种存储单元用来支持低摆幅写入。修改后的NAND解码器,不仅功耗更低,同时面积也大幅减少。对比传统单端位线的寄存器文件,低摆幅技术在读和写部分能分别降低51.15%和34.5%的功耗。后仿结果表明在十二个端口同时工作时,低摆幅策略能够降低39.4%的功耗。     

An ultrahigh-density high-speed loadless four-transistor SRAM macrowith twisted bitline architecture and triple-well shield

We have developed two schemes for improving access speed and reliability of a loadless four-transistor (LL4T) SRAM cell: a dual-layered twisted bitline scheme, which reduces coupling capacitance between adjacent bitlines in order to achieve highspeed READ/WRITE operations, and a triple-well shield, which protects the memory cell from substrate noise and alpha particles. We incorporated these schemes in a high-performance 0.18-μm-generation CMOS technology and fabricated a 16-Mb SRAM macro with a 2.18-μm² memory cell. The macro size of the LL4T-SRAM is 56 mm², which is 30% to 40% smaller than a conventional six-transistor SRAM when compared with the same access speed. The developed macro functions at 500 MHz and has an access time of 2.0 ns. The standby current has been reduced to 25 μA/Mb with a low-leakage nMOSFET in the memory cell     

A 46-ns 1-Mbit CMOS SRAM

A 1-Mb (128 K×8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8-μm CMOS process technology. Standby power is 25 μW, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8×8.5-μm² cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size is 7.6×12.4 mm²     

Pipelined architecture for fast CMOS buffer RAMs

A novel pipeline architecture for CMOS static RAMs (SRAMs) that allows operation at very high clock rates is described. Basic requirements for achieving high speed are the implementation of a hierarchical architecture and a memory cell with separate READ and WRITE data lines. The access speed of hierarchically organized memory blocks was between 2.5 and 3.5 ns. The maximum operating frequency of a 16 K pipelined hierarchical SRAM (PHSRAM) is in the range of 300 MHz. The hierarchical architecture and a seven-transistor memory cell provide a circuit using digital swings all over. Key advantages of the full-swing static logic circuitry are robustness with respect to fabrication tolerances and a high-noise immunity. Moreover, the circuit can be reduced to finer structure sizes without any redesign, since there are no critical analog circuit parts     

Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs

This paper presents a scheme for designing a memristor-based look-up table (LUT) in which the memristors are connected in rows and columns. As the columns are isolated, the states of the unselected memristors in the proposed scheme are not affected by the WRITE/READ operations; therefore, the prevalent problems associated with nanocrossbars (such as the write half-select and the sneak path currents) are not encountered. Extensive simulation results of the proposed scheme are presented with respect to the WRITE and READ operations; its performance is compared with previous LUT schemes using memristors as well as SRAMs. It is shown that the proposed scheme is significantly better in terms of WRITE time and energy dissipation for both memory operations (i.e. WRITE and READ); moreover it is shown that the READ delay is nearly independent of the LUT dimension. Simulation using benchmark circuits for FPGA implementation show that the proposed LUT offers significant improvements also at this level.     

一种用于温补晶振的EEPROM修调电路设计

设计了一种用于温度补偿晶体振荡器(TCXO)的数字修调电可擦除只读存储器(EEPROM)电路.该电路具有正常工作模式和RAM WRITE、EEPROM WRITE、EEPROM READ三种测试模式,用于TCXO中模拟补偿电压的修调.在SMIC 0.35μm工艺下,采用HSPICE工具对设计的电路进行了仿真与验证,结果表明该电路具有可靠性高和功耗低的优点.     

A flexible multiport RAM compiler for data path

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. The targeted feature is the flexibility in both layout and port organization. Fast access time and fully static and asynchronous port operation are also goals. A wide bit-word organization range including 16 b×2048 words and 72 b×512 words was also obtained. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. In addition to READ and WRITE ports, READ/WRITE ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no DC power consumption. The address access times of the generated three-port RAMs are, for example, 5.0 ns for 1 K and 11.0 ns for 32 K     

A fast 32 K/spl times/8 CMOS static RAM with address transition detection

A high-speed 256 K (32 K/spl times/8) CMOS static RAM (SRAM) is described. Precharging and equalization schemes are implemented with address-transition-detection (ATD) techniques. With a differential sensing circuitry, a 23-ns access time is achieved (at V/SUB cc/=5 V and 25/spl deg/C) for addresses and chip-select clocks. The operating current is 36 mA in the READ cycle and 28 mA in the WRITE cycle, at 10-MHz cycling frequency. A four-transistor memory cell is designed with double-polysilicon and double -metal layers to achieve high performances. Versatile redundancy schemes consisting of polysilicon laser fuses, logical circuitry, and novel enable/disable controls are designed to repair defective cells. A compensation circuit is used to optimize writing parameters for redundant columns.     

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fullypipelined architecture

The authors describe a 512 K CMOS static RAM (SRAM) with emitter-coupled-logic (ECL) interfaces which has a 2-ns cycle time and a 3.8-ns access time, both of which are valid for random READ/WRITE operations. The CMOS technology and the physical organization of the chip are briefly discussed, and the pipelined architecture of the chip is described. Detailed measurements of internal chip waveforms demonstrating 2-ns cycle time operation are presented. The impact of wire RC delays on performance is discussed. Circuit examples that demonstrate the implementation of the pipelined architecture are included. Measurements of operating margins, access time, and cycle time are outlined     

Effects of nonlinear storage capacitor on DRAM READ/WRITE

Important aspects of nonlinear storage capacitor switching and their impact on DRAM READ/WRITE operations are explained using a simple model and PSpice simulation. The voltage signal and charge-transfer rate are found to be dependent not only on the total charged stored, but also on the exact shape of the storage capacitor Q-V curve. Typical paraelectric capacitors are shown to deliver a smaller voltage signal than a linear capacitor that has the same stored charge at the operating voltage. Further, typical paraelectric capacitors have slower READ but faster WRITE compared to the linear capacitor     

A 25 ns 64K static RAM

A high-performance 64K/spl times/1-bit CMOS SRAM is described. The RAM has an access time of 25 ns with active power of 350 mW and standby power of 15 mW. The access time has been obtained by using a 1.5 /spl mu/m rule CMOS process, advanced double-level A1 interconnection technology, an equalizer circuit, and a digit line sense amplifier that is the first sense amplifier directly connected to digit lines. The WRITE recovery circuit is effective in improving WRITE characteristics, and a block selecting circuit was used for low power dissipation.     

A 45-ns 256K CMOS static RAM with a tri-level word line

A 32K words by 8-bit static RAM fabricated with a CMOS technology is described. The key feature of the RAM is a tri-level word-line, in which an automatic power down by a pulsed word-line in the READ cycle and a power saving by a middle-level word-line in the WRITE cycle are combined. This circuit technique minimizes bitline swing, shortens the precharging time, and depresses the transient current. An improved address transition detection circuit reduces the chip select access time. The sense amplifier uses internally synchronized signals for improved operation. The RAM has a typical access time of 45 ns with an active power dissipation of 7 mW. The peak transient current is less than 40 mA. A double-level polysilicon technology with a 1.3-/spl mu/m design rule allowed layout of the NMOS memory cell in an area of 116.0 /spl mu/m/SUP 2/ and the die in 49.6 mm/SUP 2/.     

A 25-ns 16K CMOS PROM using a four-transistor cell and differential design techniques

A 25-ns, 250-mW, 2K/spl times/8 PROM using a 1.2-/spl mu/m n-well CMOS technology is described. Speed and programmability are optimized by separating the READ and WRITE transistor functions in a four-transistor differential cell and using differential design techniques. For the first time, a substrate bias generator is used in an EPROM technology to improve speed and raise latch-up immunity to over 200 mA.     

Sub-1V embedded SRAM with bit-error immune dual-boosted cell technique

A sub-1 V operating SRAM based on the dual-boosted cell technique is described. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin (SNM) to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell readout current. A 0.18 mum 256 kbit SRAM macro has been fabricated with the proposed technique, which demonstrated: 0.8 V operation with 50 MHz while consuming a power of 65 muW/MHz; 400 mV read SNM at 0.8 V power supply; and a reduction by 87% in bit-error rate compared with that of a conventional SRAM     

New nibbled-page architecture for high-density DRAMs

A nibbled-page architecture which can be used to access all column addresses on the selected row address randomly in units of 8 bits at the 100 Mbit/s data rate is discussed. To realize such high-speed architecture, three key circuit techniques have been developed. An on-chip interleaved circuit has been used for the high-speed serial READ and WRITE operations. Column address prefetch and WE signal prefetch techniques have been introduced to eliminate idle time between 8 bit units. The nibbled-page architecture has been successfully implemented in an experimental 16 Mb DRAM, and 100 Mb/s operation has been achieved. The DRAM with nibbled-page mode is very effective in simplifying the design of high-speed data transfer systems     

Implementation of low-voltage static RAM with enhanced data stability and circuit speed

This paper presents a novel SRAM circuit technique for simultaneously enhancing the cell operating margin and improving the circuit speed in low-voltage operation. During each access, the wordline and cell power node of selected SRAM cells are internally boosted into two different voltage levels. This technique with optimized boosting levels expands the read margin and the write margin to a sufficient amount without an increase of cell size. It also improves the SRAM circuit speed owing to an increase of the cell read-out current. A 256 Kbit SRAM test chip with the proposed technique has been fabricated in a 0.18 μm CMOS logic process. For 0.8 V supply voltage, the design scheme increases the cell read margin by 76%, the cell write margin by 54% and the cell read-out current by three times at the expense of 14.6% additional active power. Silicon measurement eventually confirms that the proposed SRAM achieves nearly 1.2 orders of magnitude reduction in a die bit-error count while operating with 26% faster speed compared with those of conventional SRAM.     

Acoustic-surface-wave recirculating memory

An acoustic-surface-wave memory is described, operating at a bit rate of 220 MHz and storage capacity of 1280 bit per recirculation loop. The transducers are coded using orthogonal pairs of Golay complementary sequences to obtain pulse-in pulse-out behaviour. The recirculation electronics uses standard commercial logic for both the amplifier and the WRITE, READ, INHIBIT and RECLOCKING functions.     

The twin-port memory cell

A novel full-CMOS six-transistor memory cell that provides uncontested and overlapped two-port read accesses to one-cell, and concurrent READ/WRITE operations to separate cells, has been designed and functional test circuits is fabricated. This twin-port cell is based on the traditional cross-coupled inverter, but with a versatile access scheme. Balanced differential access transistors have given way to independent and complementary access transistors attached to a common readout node in the cell. Independent N-port and P-port word lines control the NMOS and PMOS access devices routing stored data to N and P bit lines, respectively. Each port has the potential of accessing a cell without interference from activities at other port even if addressing the same cell. This cell, with a complementary single bit line and access transistor per port structure, is only 11% larger than a similarly constructed conventional six-transistor single-port CMOS cell.