高精度ADC转换核的设计

在DSP的A/D转换电路中,转换核电路是整个电路的核心模块,包括时钟电路、采样保持电路（S/H）、MDAC电路、比较器电路、子ADC译码电路、冗余位数字校正电路等。同时转换核电路通常又是整个A/D电路中功耗最大的模块,其性能直接决定了整个A/D转换器的性能。文章介绍了一种l2位25MS/s转换核电路设计。该电路采用TS...     

千兆以太网卡芯片A/D转换电路的设计与实现

介绍了一种用于千兆以太网卡芯片的8位125 MS/s CMOS流水线A/D转换电路的设计,包括体系结构设计、电路设计与仿真、版图设计。该A/D转换电路经过TSMC 0.13μm 1P8MCMOS工艺验证,工作电压为1.5 V/2.7 V。芯片测试结果表明,设计的A/D转换电路能够满足千兆以太网卡芯片的性能要求。     

高精度宽范围数控电流源模块设计

文章设计并制作了一个高精度宽范围数控电流源模块,该模块由逻辑控制电路、D/A转换电路、压控恒流源电路和电压监测保护电路组成,采用可编程逻辑解析处理器的控制字,经过D/A转换控制压控恒流源电路输出电流,同时输出电流通过采样电阻转换成电压送至A/D转换,并与预设值进行比较,以实现高精度、高量程的电流输出。设计的该电流源模块能够满足高精度航空电机的控制需求,具有控制精度高、输出范围宽,降低了设备的重量和体积等优点。     

一种单片机双极模拟信号A/D转换的电路设计

实现 A/D转换通常需要使用A/D转换芯片,而单片机内置的A/D模块只能接收单极模拟信号。文中介绍了一种使Freescale单片机A/D转换模块能够接收双极型模拟信号的电路设计,文中电路采用对称设计,扩大了A/D转换的量程,提高了A/D转换的分辨率。     

数字电压电流表的软件设计

主要采用ATMEGA8芯片和一些外设电路来完成数字电压电流表的设计,能够对输入的0～20 V电压及0～5A电流进行测量,并通过一个四位一体的8段LED数码管进行动态显示.测量精度为0.1％,还可以与PC进行串行通信.设计主要由五大模块组成:量程自动转换模块、A/D模数转换模块、单片机控制模块、显示模块和通信模块.采用ATmega8单片机主控,内设A/D转换器,可直接对输入量进行A/D转换控制.     

SN8P1907微控制器在称重系统中的应用

SN8P1907是一款8位CMOS低功耗微处理器,它内置16位A/D转换模块和4 COM、12SEGMENT液晶驱动模块.文中给出了采用SN8P1907单片机设计小型称重系统的具体方法,该方法可以节省外置A/D转换器件和外部液晶驱动器件;同时具有设计程序简单等优点,因而是一种性价比很高的设计方案.     

Apple—Ⅱ微机—色谱仪联机数据处理的16位A／D转移电路

本文介绍的16位A／D转换电路，是专为AppleⅡ与色谱仪联机数据处理而设计的，电路采用两片8位的D／A芯片，用EPROM替代转换中的逐位逼近寄存器，实现16位A／D转换，并采用A／D转换量程扩充处理方法，使该电路在处于小信号输入状态下的转换分辨率达到20位字长。     

ADC中高精度转换序列发生器的设计

在信号处理过程中,自然界的模拟信号首先要经过A/D转换器(ADC)变换成数字信号,送到DSP中。文章设计了一种高精度的转换序列发生器,能分别单独处理8位数据,并行后能处理16位数据。这意味着ADC每收到一个启动转换请求,模块可以自动执行多次转换。对于每一次转换,可以通过模拟多路开关选择16个可用输入通道中的任何一个。转换结束后,所选通道的转换结果被保存在相应的结果寄存器中。也可以对同一个通道采样多次,允许用户使用"过采样",其较传统的单次采样转换结果提供了更高的精度。该设计为高精度DSP的设计提供了良好的技术基础。     

数字发射机A/D(模数)转换技术研究

我们知道数字调幅(DAM)中波发射机里包含有A/D(模数)转换电路,其主要功能是实现时间上连续模拟信号向时间上离散数字信号的转换。经过A/D转换以后的数字信号就可以进行调制编码,从而实现对射频功放的控制,同时使"数字幅度调制"形成。再经过D/A(数模)转换实现数字信号向模拟信号的转换。该技术的应用,能够使数字调幅(DAM)中波发射机取得最佳音频效果。     

一种PC机A/D转换接口的制作

<正> 计算机只能识别二进制数字信号。当计算机用于模拟信号检测时,需要配置A/D(模/数)转换接口电路,将模拟信号转换成二进制数字量送入微机。商品化的A/D转换接口价格在数百元以上,一般电脑爱好者难以问津。能否自己动手制作A/D转换接口电路呢?答案是肯定的。这里介绍一种笔者设计并已在科研中应用的A/D转换接口电路,它通过PC机打印机插座与主机相连,无需打开机箱插卡,具有成本低廉(元器件成本20多元)、制作方便等特点,适用于各类PC机。     

Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.     

单片机与串行AD转换器TLC0834的接口设计

TLC0834是TI公司生产的八位逐次逼近模数转换器 ,具有输入可配置的多通道多路器和串行输入方式。文中以AT89C51CPU为核心 ,采用LTC0834八位串行A/D转换器设计了一个可将模拟信号转换为数字信号的电路     

用于生物医学成像的多通道流水线数字化电路设计

针对生物医学成像中前端读出电路多通道以及要求高速数字化的特点,设计了一个16通道的流水线数字化电路.整个电路由模拟多路选择器、单端转差分电路、8-bit 25Ms/s 1.5bit/stage流水线ADC以及数据输出模块组成.模数转换和数据输出在两相邻时间窗口内采用流水线方式进行.电路采用TSMC 0.18μm mixed signalCMOS工艺实现.电路仿真结果表明,流水线ADC的DNL为-0.62/0.67LSB,INL为-0.39/0.72LSB,SNR为45.99dB,ENOB为6.03bit,该电路能够在两个相邻时间窗口内完成16通道的信号数字化并输出,满足系统设计要求.     

数字温度计的设计

根据目前温度传感器的数字化和温度表的发展现状,研究和设计了一种基于51系列单片机的数字温度计。数字温度计控制电路的核心是基于51系列中ATMEL公司的8位单片机AT89C51。测温传感器采用了新型单线数字温度传感器DS18B20,不需要专用A/D转换电路来实现温度量由模拟量到数字量的变换,并可与单片机直接连接。同时,系统的显示部分采用4位LED串行动态显示,用74LS373的输出信号分别作为LED的位驱动信号和段驱动信号。该数字温度表实现了对温度采集、处理、实时显示,并可实现对测温系统的温度控制。     

Monolithic optical position encoder with on-chip photodiodes

A system that combines light sensors and analog and digital parts on the same CMOS chip has been fabricated. The optical and electrical properties of various photodiodes, which are fully compatible with a standard CMOS technology, are discussed. The current comparators use CMOS-compatible lateral bipolar transistors. The optical encoder also comprises a signal processor for code conversion, a serial or parallel output, and a self-test function. A 14-channel circuit which senses light signals at 880 nm with a power of 0.3-3 mW/cm² has been fabricated. Response time is shorter than 1 μs at all illumination levels. This circuit operates in the temperature range -55 to +125°C. Its current consumption is 8 mA at 5 V     

A single-chip CMOS analog/digital mixed NTSC decoder

A single-chip CMOS LSI that integrates all analog-to-digital (A/D), digital-to-analog (D/A), peripheral, and digital signal processing circuits necessary for a digital National Television System Committee (NTSC) signal decoder is described. The LSI chip accepts composite NTSC video signals in analog form, digitizes them using the on-chip A/D converter, converts them to component RGB signals, and then converts the signals to analog form by using the on-chip D/A converters. The development of circuits that maximize use of the input digital data is discussed. A 6-b A/D circuit is used to reduce the circuit size. Circuits that help maintain acceptable picture quality despite 6-b resolution were developed. Besides analog NTSC signal input and RGB signal output, the IC can also input and output digital NTSC signals, Y/C (luminance, chrominance) signals, and RGB signals. Applications of the LSI are presented     

基于FPGA的双通道汽车涡轮增压叶片温度采集卡研制

一种应用于汽车涡轮增压器叶片温度检测的双通道数据采集卡,该卡由峰值检测、串行A/D构成模拟电路和由FPGA构成整个数字电路而组成。重点设计了FPGA内部串并转换电路和FIFO,经仿真和实验验证,串并转换和FIFO的应用大大简化了采集卡的复杂程度,提高了系统的可靠性和稳定性,在信号高速处理方面具有一定的应用价值。     

A Serial Input/Output Circuit with 8 bit and 16 bit Selection Modes

This paper presents a serial interface circuit that permits selection of the amount of data converted from serial‐to‐parallel and parallel‐to‐serial and overcomes the disadvantages of the conventional serial input/output interface. Based on the selected data length operating mode, 8 bit or 16 bit serial‐to‐parallel and 8 bit or 16 bit parallel‐to‐serial conversion takes place in data blocks of the selected data length.     

A high-speed 7 bit A/D converter

A 7 bit two-step parallel A/D converter has been designed using a new quantizer-subtractor circuit. The small delay in the new circuit allows digital signal sampling by latching comparators. A sample and hold unit is not needed which results in a fully integrable A/D function. Analog input signals up to 5 MHz can be digitally sampled with sampling frequencies up to 50 MHz. A double layer metallization process is used to reduce the die size to 2.4/spl times/2.5 mm.     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.