Optically-controlled ion-implanted GaAs MESFET characteristic withopaque gate

An analytical modelling has been carried out for an ion-implanted GaAs MESFET having a Schottky gate opaque to incident radiation. The radiation is absorbed in the device through the spacings of source, gate, and drain unlike the other model where gate is transparent/semitransparent. Continuity equations have been solved for the excess carriers generated in the neutral active region, the extended gate depletion region and the depletion region of active (n) and substrate (p) junction. The photovoltage across the channel and the p-layer junction and that across the Schottky junction due to generation in the arc region of the gate depletion layer are the two important controlling parameters. The I-V characteristics and the transconductance of the device have been evaluated and discussed     

Photon generation in forward-biased silicon p-n junctions

Photons are generated by forward biasing a silicon p-n junction at 10^-5∼ 10^-4quantum efficiency through radiative recombination. At large distances from the forward-biased junction, leakage currents of magnitudes significant for some VLSI circuits can appear due to the substrate minority carriers generated by the photons. The effective decay length of the measured leakage current is about several hundred to one thousand micrometers. The effects of forward biasing an input node or a parasitic lateral bipolar transistor are, therefore, longer ranged than commonly assumed.     

Characterization of leakage currents in long-lifetime capacitors

The purpose of this paper is to present a new procedure that yields the material parameters characterizing leakage currents in MOS devices (generation lifetime in the depletion region τg, recombination lifetime in the bulk τr, interfacial generation velocity S) by means of the linear-sweep technique at different temperatures and at different depths of the depletion region. This characterization method is applied to long-lifetime MOS capacitors for which different contributions to the leakage current (generation in the depletion region, diffusion from the neutral bulk and interfacial generation) are of the same order of magnitude.     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low     

Generation mechanism of gate leakage current due to reverse-voltagestress in i-AlGaAs/n-GaAs HIGFETs

Device degradation characterized as an increase in the gate leakage current due to continuous reverse-voltage stress was investigated for a 0.35-μm WSi gate i-AlGaAs/n-GaAs doped channel HIGFET (heterostructure insulated-gate field-effect transistor). The gate leakage current, which was dominated by a hole current generated by impact ionization, was found to increase after the application of a gate-to-drain voltage of -6 V for a certain period. The occurrence of the impart ionization was evidenced by the generation of a substrate current and by the negative temperature coefficient of the gate current. The degradation was retarded at an elevated temperature, indicative of hot-carrier-related degradation. The degraded device also showed an ohmic-like gate leakage current. Subsequent annealing at temperatures above 300°C significantly restored the current-voltage (I-V) characteristics. From these observations, a degradation model was developed in which hot holes generated by impact ionization are trapped in the insulator/semiconductor interface, contracting the surface depletion region and thereby increasing the electric field near the gate-edge. A surface treatment using CF₄ plasma was used to suppress the degradation. An FET fabricated using this treatment showed a remarkable decrease in degradation     

Creation and termination of substrate deep depletion in thin oxide MOS Capacitors by charge tunneling

Deep depletion in both p-type and n-type substrates can be induced by minority carriers tunneling away from the substrate. When this occurs, tunneling current becomes saturated at the rate of carrier generation in the substrate, with the excess applied voltage dropped across the deep-depletion region. We present a quantitative model for this phenomenon based on balancing the tunneling current and the space-charge generation current. Conversely, the usual transient deep depletion in n-type substrate MOS capacitors can be terminated by tunneling-induced electron-hole pair generation, except for those with ultrathin oxides (<40 Å).     

A field-funneling effect on the collection of alpha-particle-generated carriers in silicon devices

We studied the transient characteristics of charge collection from alpha-particle tracks in silicon devices. We have run computer calculations using the finite element method, in parallel with experimental work. When an alpha particle penetrates a pn-junction, the generated carriers drastically distort the junction field. After the alpha particle penetration, the field, which was originally limited to the depletion region, extends far down into the bulk silicon along the length of the alpha-particle track and funnels a large number of carriers into the struck junction. After a few nanoseconds, the field recovers to its position in the normal depletion layer, and, if the track is long enough, a residue of carriers is left to be transported by diffusion. The extent of this field funneling is a function of substrate concentration, bias voltage, and the alpha-particle energy.     

Thermally generated leakage current mechanisms of metal-induced laterally crystallized n-type poly-Si TFTs under hot-carrier stress

Mechanisms of thermally generated leakage current have been systematically studied for metal-induced laterally crystallized n-type polycrystalline silicon thin film transistors under the hot-carrier stress. Various mechanisms of thermally generated leakage current are identified by both forward and reverse modes. The decrease of thermally generated leakage current is attributed to the depletion region modulation effect, which results from its shrinkage. While the increase of thermally generated leakage current is caused by the increase of the donor trap density, its increment relative to the initial one follows the Schottky model in the forward mode. Overall, the depletion region modulation effect dominates and the thermally generated leakage current decreases.     

Multiplication noise in uniform avalanche diodes

A general expression is derived from which the spectral density of the noise generated in a uniformly multiplying p-n junction can be calculated for any distribution of injected carriers. The analysis is limited to the white noise part of the noise spectrum only, and to diodes having large potential drops across the multiplying region of the depletion layer. It is shown for the special case in whichbeta = kalpha, wherekis a constant and α and β are the ionization coefficients of electrons and holes, respectively, that the noise spectral density is given by2eI_{in}M^{3}[1 + (frac{1 - k}{k})(frac{M - 1}{M})^{2}]where M is the current multiplication factor and Iinthe injected current, if the only carriers injected into the depletion layer are holes, and by2eI_{in}M^{3}[1 - (1 - k)(frac{M - 1}{M})^{2}]if the only injected carriers are electrons. An expression is also derived for the noise power which will be delivered to an external load for the limitM rightarrow infin.     

从多子角度阐述p-n结理论

传统方法在分析p-n结理论时仅仅关注了过剩少子的扩散电流,但是随着其浓度梯度的降低,扩散电流趋于零,则电流的连续性将难以理解。另外,如果仅仅考虑过剩少子的注入,则无法理解"中性区"的电中性(即电中性条件将被破坏)。针对以上矛盾,以基本的器件物理为基础,分析并得到过剩多子必然存在于中性区,且其分布和数量与过剩少子相同,因而过剩多子的扩散电流也参与p-n结的电流输运。在充分考虑过剩多子的基础上,对p-n结的工作机理可以有更好、更深刻的理解。理想二极管方程在一些假设下仅仅考虑了空间电荷区两边过剩少子的扩散电流,提供了一个很巧妙地计算总电流的方法。     

The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.     

Alternative mechanism for substrate minority carrier injection in MOS devices operating in low level avalanche

The mechanism proposed by Matsunaga et al. to explain the injection of minority carriers into the substrate of a saturated n-channel MOST cannot account for the size of the observed current. An alternative mechanism is suggested based on optical generation of minorities by radiation emitted by hot carriers in the drain depletion region. Evidence for this mechanism is presented.     

耗尽区调制对氢化MILC Poly-Si TFT热产生漏电的影响

研究了热载流子应力下耗尽区调制效应对氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电的影响.从理论上论证了热载流子应力下氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电中的耗尽区调制效应的存在.并利用正、反向测量模式,从实验上进一步确认这种效应对氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电的影响.发现在热载流子应力下,正、反向测量模式时,氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电均随应力时间的增加而减小.但由于漏极和源极附近沟道区的表面势受热空穴注入影响的程度不同,热载流子应力下,正、反向测量模式的热产生漏电减小程度不同.理解热载流子应力下耗尽区调制效应对氢化金属诱导横向结晶多晶硅薄膜晶体管热产生漏电的影响,有助于成功设计电路.     

DC performance of deep submicrometer Schottky-gated n-channel Si:SiGe HFETs at low temperatures

N-type Schottky-gated Si:SiGe heterostructure field-effect transistors with physical gate lengths between 70 and 450nm are characterized over a wide temperature range (T=10 K...300 K) for low electric fields. The room-temperature maximum low-field transconductance increases 61% to 440 mS/mm at T=10 K for the 70-nm device. The minimum subthreshold slope is 14...19 mV/dec at T=10 K. The off-state currents I/sub OFF/ are limited by parallel conduction at high temperatures and by the gate leakage current at low temperatures. Substrate leakage currents are found to be due to generation of carriers within the drain/substrate depletion layer and only make a minor contribution to I/sub OFF/. Operation of the devices at the lowest temperature is found to result in the occurrence of the floating-body kink effect, as a consequence of substrate freeze-out and subsequent self-biasing by impact ionization currents. Low temperature characteristics exhibit a nonlinear low-field drain current dependence on the drain voltage, due to the presence of parasitic Schottky source/drain contacts. An extraction method for access resistance consistent with this phenomenon is presented.     

Forward current—Voltage and switching characteristics of p+-n-n+(epitaxial) diodes

The forward-biased current-voltage and forward-to-reverse biased switching characteristics of p⁺-n-n⁺epitaxial diodes are investigated. The manner in which the n-n⁺junction affects the flow of injected minority carriers in the epitaxial region is characterized by a leakage parameter a. Experimentally, for diodes with epitaxial film widths much less than a diffusion length, a "box" profile accurately describes the injected minority carriers in the n region. The current is found to increase with increased epitaxial width at a fixed bias. A general switching expression for epitaxial diodes is presented and the validity of the expression is shown experimentally. The experimental values of a, determined independently from the current-voltage and switching characteristics, are in good agreement and show that the leakage of the high-low junction is dominated by the recombination of minority carriers in the n-n⁺space-charge region.     

Analysis of the post-breakdown current in HfO2/TaN/TiN gate stack MOSFETs for low applied biases

A thorough analysis of the post-breakdown current-voltage characteristics in HfO₂high-κ/TaN/TiN gate stacks for low positive applied biases reveals an apparent band gap narrowing of the silicon substrate at the very location of the leakage site. This effect may be caused by the migration of gate material through the percolation path during the breakdown runaway. Additionally, the voltage dependence of the current suggests that the origin of the leakage current is thermal generation within the depletion region close to the breakdown spot. A simple analytical model to deal with this current is proposed.     

Effects of generation/recombination processes and leakage current through interfacial “punctures” on electrical characterization of unipolar directly bonded semiconductor structures

Numerical simulations have been performed to analyze the influence of generation/recombination processes and leakage current through “interfacial” punctures on the results of electrical characterization of unipolar directly bonded semiconductor junctions by the methods previously proposed by the present author [Mater. Sci. Semicond. Process. 4 (2001) 177]. Physical quantities that characterize the electrical state of the bonded junction and phenomena brought about by the generation/recombination processes in the junction (static and high-frequency conduction due to minority carriers, influence of generation/recombination processes on the interfacial charge, etc.) are discussed.     

Improved analysis of pulsed C-t measurements on silicon MOS capacitors

A modified analysis of the pulse response of silicon MOS capacitors is presented which takes into account the lateral spreading of the depletion region around the gate area. Two aspects of this lateral depletion region which have previously been ignored, namely the bulk generation and space charge in this region, are taken into account and used to explain the experimentally observed dependence of the capacitor relaxation time on the device aspect ratio. The analysis allows the bulk lifetime to be obtained more accurately and also enables the surface recombination velocity resulting from a particular device processing schedule to be estimated. The results obtained agree well with those determined from junction leakage current measurements and the relevance of the lateral edge effect to the characteristics of a more complex charge coupled device has been discussed.     

基于结模型的极化石英玻璃内建电场分析

用多载流子模型分析玻璃的热极化过程及其内部耗尽层的形成,极化电场的作用使载流子在玻璃内的迁移及由外界的注入最终形成交替的电荷分布,形成类似两个相向p-n结的结构。针对几种典型的p-n结电荷分布形式,计算了相应内建电场及二阶非线性极化率,极化完成后产生的宏观非线性效应主要由钠离子耗尽形成的突变结电场(~3′109V/m)决定,二阶非线性极化率的数值在0.2~1.2pm/V之间,耗尽区分布在阳极表面下25mm的范围。     

Leakage current modeling of test structures for characterization of dark current in CMOS image sensors

In this paper, we present an extensive study of leakage current mechanisms in diodes to model the dark current of various pixel architectures for active pixel CMOS image sensors. Dedicated test structures made in 0.35-/spl mu/m CMOS have been investigated to determine the various contributions to the leakage current. Three pixel variants with different photodiodes-n/sup +//pwell, n/sup +//nwell/p-substrate and p/sup +//nwell/p-substrate-are described. We found that the main part of the total dark current comes from the depletion of the photodiode edge at the surface. Furthermore, the source of the reset transistor contributes significantly to the total leakage current of a pixel. From the investigation of reverse current-voltage (I-V) characteristics, temperature dependencies of leakage current, and device simulations we found that for a wide depletion, such as n-well/p-well, thermal Shockley-Read-Hall generation is the main leakage mechanism, while for a junction with higher dopant concentrations, such as n/sup +//p-well or p/sup +//n-well, tunneling and impact ionization are the dominant mechanisms.