Robust Design of Basic Low Voltage CMOS Transconductors

Two new low voltage transconductors are introduced and the statistical design of these transconductors are presented. The circuits operate in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response surface methodology and design of experiment techniques are used as statistical VLSI design tools together with the statistical MOS (SMOS) model. The response surfaces obtained for the two transconductors show the trade-off between area and functional yield. Using these contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours also provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.     

Robust Design of Basic Low Voltage CMOS Transconductors

Two new low voltage transconductors are introduced and the statistical design of these transconductors are presented. The circuits operate in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response surface methodology and design of experiment techniques are used as statistical VLSI design tools together with the statistical MOS (SMOS) model. The response surfaces obtained for the two transconductors show the trade-off between area and functional yield. Using these contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours also provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.     

Low voltage analog circuit design techniques

Analog signal processing is fast and can address real world problems. The applications of battery powered analog and mixed mode electronic devices require designing analog circuits to operate at low voltage levels. In this paper, some of the issues facing analog designers in implementing low voltage circuits are discussed, and possible low voltage design techniques are examined. The authors describe briefly almost all low voltage design techniques suitable for analog circuit structures along with their merits and demerits     

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.     

A comparative study of glitch-free true single-phase clocked D flip-flop circuits at low supply voltage

This paper investigates the characteristics and performances of several true single-phase clocked (TSPC) D flip-flops (D-FFs) at low supply voltage. We propose a new glitch-free D-FF for low-voltage operation. Since the dynamic power consumption in CMOS is proportional to V_dd², decreasing the supply voltage yields a large reduction in power consumption. The main design objectives for these circuits are glitch-free operation and low power consumption at low supply voltage. The proposed D-FF circuit has been compared with previously known circuits and has been shown to provide superior performance. All circuits in this paper have been simulated using HSPICE with a 0.4-μm CMOS technology at a 2-V supply voltage. An analysis of a serial pipeline multiplier design establishes the superiority of the proposed circuit in that application.     

A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V

This paper describes circuit design and measurement results of our newly developed InGaP/GaAs-HBT MMIC power amplifier (PA) module which can operate with 2.4-V low reference and low supply voltages of its on-chip bias circuits. To achieve the low-reference voltage operation, the following two new circuit design techniques are incorporated into the power amplifier: 1) AC-coupled, divided power stage configuration with two different kinds of bias feeding (voltage and current drive and only current drive) and 2) successful implementation of a diode linearizer built in the power stage. Theses two techniques allow the PA to offer smooth output transfer characteristics over a wide temperature range. Measurement results done under the conditions of 900 MHz, a 3.5-V collector voltage for power stage, and 2.4-V reference and collector voltages for the bias circuits show that the PA module meets J-/W-CDMA power and distortion requirements sufficiently over a wide temperature range from -10degC to 90degC while keeping a low quiescent current of less than 65 mA. For J-CDMA modulation, the module can deliver a 27.5-dBm output power (P_out), a 40% PAE, and a -50-dBc ACPR, while a 28-dBm P_out, a 42% PAE, and a -42-dBc ACLR are achieved for W-CDMA modulation.     

A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR

We discuss a design technique that makes possible the operation of track-and-hold (T/H) circuits with very low supply voltages, down to 0.5 V. A 0.5-V 1-Msps T/H circuit with a 60-dB SNDR is presented. The fully differential circuit is fabricated in the CMOS part of a 0.25-mum BiCMOS process, with standard 0.6-V V_T devices, and uses true low-voltage design techniques with no clock boosting and no voltage boosting. The T/H circuit has a measured current consumption of 600 muA     

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.     

Switched-opamp: an approach to realize full CMOS switched-capacitorcircuits at very low power supply voltages

The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from the standard switched-capacitor technique, is presented. It is called switched-opamp because it is based on the replacement of the critical switches with opamps which are turned on and off. This technique results in a true, very low voltage operation without the need for voltage multipliers. As an example, a second order lowpass switched-capacitor filter is implemented in the switched-opamp technique. This filter operates with only a 1.5 V power supply. It is realized in a 2.4-μm CMOS process with V_T=±0.9 V. It has a measured total harmonic distortion of -60 dB for a signal swing of 600 mV_ptp and a powerdrain of only 110 μW     

Low-voltage low-power improved linearity CMOS active resistor circuits

A tutorial of CMOS active resistor circuits will be presented in this paper. The main advantages of the proposed implementations are the improved linearity, the small area consumption and the improved frequency response. In order to improve their linearity, improved performances linearization techniques will be proposed, with additional care for compensating the errors introduced by second-order effects. Design techniques for minimizing the silicon area consumption will be further presented and FGMOS (Floating Gate MOS) transistors will be used for this purpose. The frequency response of the circuits is very good as a result of biasing all MOS transistors in the saturation region and of a current-mode operation of an important part of their blocks. Additionally, small changing in each design allows to obtain negative controllable equivalent resistance circuits. The circuits are implemented in CMOS technology, SPICE simulations confirming the theoretical estimated results, showing small values of the linearity error (under 0.15% for the best design) for an extended input range and for a supply voltage equal with ±3 V. The proposed circuits respond to low-voltage low-power requirements, their design being adapted to the continuous degradation of the model quality associated with the evolution toward latest nanotechnologies.     

Exploring the design space of mixed swing quadrail for low-powerdigital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2× improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 μm process are presented to demonstrate up to 2,92× energy/operation savings for optimized mixed swing circuits compared to static CMOS     

用Topswitch芯片设计的反激式开关电源

Topswitch系列芯片是Power Integration公司生产的开关电源专用集成电路。它将脉宽调制电路(PWM)与高压MOSFET开关管及驱动电路等集成在一起。使用该芯片设计的小功率开关电源。可大大减少外同电路，降低成本，提高可靠性。本文介绍了Topswitch系列芯片的工作原理及用该芯片制作的30W反激式开关电源，并就电路设计中的关键问题做了详解。     

A precision variable-supply CMOS comparator

Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.     

Circuit techniques for 1.5-V power supply flash memory

We describe circuit techniques for a Flash memory which operates with a V_DD of 1.5 V. For the interface between the peripheral circuits and the memory core circuits, two types of level shifter circuits are proposed which convert a V_DD level signal into the high voltage signals needed for high performance. In order to improve the read performance at a low V_DD, a new self-bias bitline voltage sensing scheme is described. This circuit greatly reduces the delay's dependence on bitline capacitance and achieves 19 ns reduction of the sense delay at low voltages. Multilevel storage sensing with this circuit is also discussed     

低压低功耗模拟集成电路的发展

集成电路的低压低功耗设计已成为当今微电子领域研究的热点。介绍了集成电路(IC)低功耗设计问题的产生，在讨论IC的低功耗设计技术基础上，重点论述了模拟IC的低压低功耗设计问题，介绍了国内外最新的若干模拟IC低压低功耗解决方案及其特点以及实现方法。     

Reverse-body bias and supply collapse for low effective standby power

Integrated circuits fabricated on a low-leakage process typically display lower performance due to the high threshold voltage (V/sub t/) transistors. Higher performance microprocessors sacrifice power efficiency by decreasing V/sub t/. We show that a processor built on a low V/sub t/ process can achieve the power-per-computation characteristics of one built using a high V/sub t/ process, by using a "drowsy" mode combining reverse body bias (RBB) and voltage collapse when idle. This approach also allows for higher peak performance, if needed. A simple power model is shown to accurately match the measured data; high-operational frequency is demonstrated when in active operation. The circuit techniques used to provide the RBB mode of operation are described and compared with other techniques such as multi-threshold CMOS. While both techniques can be effective for logic, the design effort for RBB is shown to be smaller, while reducing embedded static random access memory standby power without added size.     

平板显示器驱动芯片高低电压转换电路

LCD、PDP、VFD等各类平板显示器已越来越受到人们关注与喜爱,但大多数平板显示器需要专用的功率驱动芯片来驱动其发光显示,各类专用功率驱动芯片又离不开高低电压转换电路,高低电压转换电路性能的好坏直接影响到驱动芯片的稳定性和功耗等。通过比较平板显示器驱动芯片的几种典型高低压转换电路,设计出一种带有电流源的CMOS型高低压转换电路,它具有最佳的性能指标,该电路不但可以为平板显示器驱动芯片使用,还可以作为其他各类驱动芯片的高低压转换模块使用,最后给出一种具体的平板显示驱动芯片高压CMOS器件结构。     

单片化低压低功耗Si CMOS运算放大器的实现

基于新型的折叠共栅共源PMOS差分输入级拓扑、轨至轨AB类低压CMOS推挽输出级模型、低压低功耗LV/LP技术特别考虑和EDA平台的实验设计与模拟仿真,并设计配置了先进的Si 2 mm P阱硅栅CMOS集成工艺技术。已经得到一种具有VT = 0.7 V、电源电压1.1~1.5 V、静态功耗典型值330 mW、75 dB开环增益和945 kHz单位增益带宽的LV/LP运算放大器。该运放可应用于ULSI库单元和诸多相关技术领域,其实践有助于Si CMOS低压低功耗集成电路技术的进一步开发与交流。