A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection

This paper presents a comprehensive modelling methodology for the electromagnetic immunity of integrated circuits (ICs) to direct power injection (DPI). The aim of this study is to predict the susceptibility of ICs by the means of simulations performed on an appropriate electrical model of different integrated logic cores located in the same die. These cores are identical from a functional point of view, but differ by their design strategies. The simulation model includes the whole measurement setup as well as the integrated circuit under test, its environment (PCB, power supply) and the substrate model of each logic core. Simulation results and comparisons with measurement results demonstrate the validity of the suggested model. Moreover, they highlight the interest of the aforementioned protection strategies against electromagnetic disturbances.     

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFLcircuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 μm were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems     

Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits

This paper presents a comparative study of susceptibility reduction techniques for electromagnetic interference (EMI) in digital integrated circuits (ICs). Both direct power injection (DPI) and very-fast transmission-line pulsing (VF-TLP) methods are used to inject interference into the substrate of a single test chip. This IC is built around six functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low emission design rules. The ranking of three of these cores in terms of electromagnetic immunity is then compared with the one of their radiated emission, thanks to near-field scanning (NFS) measurements. This leads to the establishing of design guidelines for low EMI in digital ICs.     

Failure Analysis enhancement by evaluating the Photoelectric Laser Stimulation impact on mixed-mode ICs

The mixed-mode ICs (Integrated Circuits), by involving multiple functions (digital, analog, RF, power) inside one device, are becoming more compact and useful. At the same time, their developments and Failure Analysis (FA) are more and more complex: test, diagnostic and defect localization steps are harder and longer in time. Each step needs to be improved as far as defect localization is concerned. Several techniques based on emission microscopy, electron beam, direct probing or laser stimulation have been developed and introduced to follow these ICs evolutions. The most recent evolution in the laser stimulation field has been the introduction of several dynamic laser stimulation techniques aimed to localize defects or weakness regions inside functional but failing ICs (environmental marginalities related to temperature, frequency, voltage, etc.). This paper deals with the use of dynamic photoelectric laser stimulation techniques applied on mixed-mode ICs where the major difficulty is due to their considerable intrinsic sensitivity. Indeed, the analog circuitry is more sensitive than the digital circuitry since a slight change in an electrical parameter can trigger a functionality failure. This property limits the defect localization because of the complex interpretation of the results, the laser stimulation mapping. We propose to help the failure analyst by coupling the dynamic laser stimulation mapping with the photoelectric impact simulations run on a previously analyzed structure. The goal is to predict and interpret the laser sensitivity mapping so to isolate the defective areas in the analog devices.     

Modeling and analysis of power distribution networks for Gigabit applications

As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) accurately. This paper presents the modeling, simulation, and characterization of the PDN in a high-speed printed circuit board (PCB) designed for chip-to-chip communication at a data rate of 3.2 Gbps. The test board consists of transmitter and receiver chips wirebonded onto plastic ball grid array (PGBA) packages on a PCB. In this paper, a hybrid method has been applied for analysis, which consists of the transmission matrix method (TMM) in the frequency domain and macromodeling method in the time domain. As an initial step, power/ground planes have been modeled using TMM. Then, the macromodel of the power/ground planes has been generated at the desired ports using macromodeling. Finally, the macromodel of the planes, transmission lines, and nonlinear drivers have been simulated in standard SPICE-based circuit simulators for computing power supply noise. In addition to noise computation, the self and transfer impedances of power/ground planes have been computed and the effect of decoupling capacitors on power supply noise has been analyzed. The methods discussed have been validated using hardware measurements.     

Design considerations for low-voltage on-board DC/DC modules fornext generations of data processing circuits

By reducing the power supply voltage, a higher speed, lower power consumption, and higher integration density of data processing ICs can be achieved. Presently, a variety of ICs operating from 3.3 V are available. Next generations of ICs are expected to work even with lower voltages, i.e., in the 1-3 V range, to further enhance their speed-power performance. At the same time, during transients, these new generations of data ICs will present very dynamic loads with high current slew rates. As a result, they will require point-of-load power supplies in order to minimize the effects of the interconnection parasitics. These onboard power supplies will be derived from the existing voltages available in the system (usually 5 or 12 V), and will be required to have high power densities, high efficiencies, and good transient performance. This paper presents design considerations for these on-board power supplies and discusses their performance limits imposed by various circuit and system parasitics     

电源管理器件输出电压精度的分析

电源管理芯片的高精度电压输出，是电源管理技术的一个重要课题，以LDO稳压器为基础，详细分析了基准电压漂移、误差放大器电压漂移等影响电源电压输出精度的主要因素。     

2.5Gbps发接器系统均衡器电路的设计

采用片上可编程均衡技术 ,设计了用于数据率为 2 .5 Gbps发接器系统接收端的均衡器电路。电路采用 0 .1 8μm标准 CMOS工艺和 1 .8V单电源。用 UMC模型 Cadence Spectre S软件进行了仿真 ,电路在 0～1 2 5°C范围内 ,三种工艺角和电源电压变化± 1 0 %的条件下能够正确地工作。在 1 .8V电源、75°C和 tt工艺角条件下 ,电路的总功耗为 40 m W。     

Local thermal probing to detect open and shorted IC interconnections

A new failure analysis technique has been developed for backside and frontside localization of open and shorted interconnections on ICs. This scanning optical microscopy technique takes advantage of the interactions between IC defects and localized heating using a focused infrared laser (λ=1340 nm). Images are produced by monitoring the voltage changes across a constant current supply used to power the IC as the laser beam is scanned across the sample. The method utilizes the Seebeck Effect to localize open interconnections and Thermally-Induced Voltage Alteration to detect shorts. The interaction physics describing the signal generation process and several examples demonstrating the localization of opens and shorts are described. Operational guidelines and limitations are also discussed.     

光电对抗仿真试验技术

文中介绍了美国空军电子战评估系统、陆军导弹司令部先进仿真中心以及海军仿真实验室的光电仿真试验设施及其相关技术,将美国目前所使用的光电仿真器归纳为两种类型：一种是光学机械式,另一种是计算机生成图像仿真系统。指出计算机红外成像彷真是未来光电仿真试验的发展趋势,介绍了电阻阵、二极管激光器、基于光纤的热转换器三种实现方案,建议我国光电仿真试验建设应以计算机景象生成为基础的通用仿真器为主,同时兼顾技术成熟的光机式仿真器,走二者相结合的道路。     

Spectral and energy efficient cognitive radio‐aided heterogeneous cellular network with uplink power adaptation

In future heterogeneous cellular networks, cognitive radio compatible with device to device communication technique can be an aid to further enhance system spectral and energy efficiency. The unlicensed smart devices (SDs) are allowed to detect the available licensed spectrum and utilise the spectrum resource which is detected as not being used by the licensed users. In this work, we propose such a system and provide comprehensive analysis of the effect of selection of SDs' frame structure on the energy efficiency, throughput and interference. Moreover, uplink power control strategy is also considered where the licensed users and SDs adapt the transmit power based on the distance from their reference receivers. The optimal frame structure with power control is investigated under high‐signal‐to‐noise ratio (SNR) and low‐SNR network environments. The impact of power control and optimal sensing time and frame length, on the achievable energy efficiency, throughput and interference are illustrated and analysed by simulation results. It has been also shown that the optimal sensing time and frame length which maximizes the energy efficiency of SDs strictly depends on the power control factor employed in the underlying network such that the considered power control strategy may decrease the energy efficiency of SDs under very low‐SNR regime. Copyright © 2016 John Wiley & Sons, Ltd.     

激光淬火工艺参数对层深及硬度影响敏感性研究

为了了解激光功率和扫描速度变化对淬火层深和表面硬度影响的敏感性,从实验和理论模拟两方面开展了相关研究.在满足激光输入能量相等的条件下,采用按相同倍率提高激光功率或降低扫描速度的方法,研究淬火层深和表面硬度的相应变化.研究结果表明,按相同倍率改变激光功率或扫描速度均会对层深产生明显影响,而激光功率变化的影响更大;但仅改变激光功率或扫描速度不会对表面硬度产生很大影响,相对而言,扫描速度变化对表面硬度的影响略大一些.进一步通过对激光扫描温度场及加热、冷却速度的理论模拟,对上述研究结果做出了合理的理论解释.     

利用速率方程分析光纤激光器相干耦合系统的尝试

尝试采用稳态速率方程,分析了由一个光纤耦合器连接起来的、两个掺Er光纤激光器组成的相干耦合系统.考虑到设置在光纤耦合器的一个输出端口的公共反射镜还担负着实施两个激光器间的相互注入的功能,利用光纤耦合器的变换矩阵以及光场相干叠加的要求,可以确定激光器速率方程组满足的边界条件.在进行合理的近似处理后,把速率方程组转化为代数方程组.利用这些结果分析了系统的一些特性,比如耦合器的分光比和不同泵浦功率对输出功率的影响等.     

Plugging the global power leak [appliance standby mode powerreduction]

Standby mode is a convenient but extremely wasteful feature of many electronics products. The authors describe how the GreenChip family is helping to produce a more environmentally friendly switched mode power supply. The new ICs implement an extensive set of power management functions focused on improving the efficiency of the standard flyback supply in standby mode. They achieve this by introducing three special modes of operation, referred to as burst-mode, off-mode and low-frequency mode. Use of GreenChip devices can typically reduce standby power to 2-3 W, and for a slight increase in cost this can be brought down to less than 500 mW. Along with these green features, the ICs have been designed to simplify the design task and reduce the component count, thereby addressing environmental concerns while reducing overall product costs. A new development in high-voltage IC technology based on a thin-layer silicon-on-insulator (SOI) process has been announced by Philips Semiconductors. This technology, known as EZ-HV-SOI, is expected to allow significant improvements and enhancements in the next generation of GreenChip controllers     

Simulating the exposure of ICs to voltage surges caused by nuclear explosions

A uniform strategy is developed for testing discrete semiconductor devices and ICs for voltagesurge hardness, allowing comparison of differing models including ICs of high functional complexity. Performance specifications are defined, justified, and implemented for a voltage-surge simulator intended for electrical-overstress hardness tests of ICs. On this basis, a test bed is designed and built for evaluating the hardness of advanced ICs to voltage-surge effects, whether transient or permanent. A procedure is developed for predicting the electrical-overstress hardness of ICs, which enables one to detect both out-of-tolerance and functional failures during testing. The procedure and the test setup are validated by experiments with specific ICs.     

A comparison of Nd:YAG fundamental and second-harmonic Q-switched laser-beam lifetime doping in single-crystal silicon

Silicon devices including bipolar transistors, junction diodes, and MOS capacitors were scanned by aQ-switched Nd:YAG (1.06 µm) and frequency-doubled Nd:YAG (0.53 µm) radiations under various conditions. The electrical characteristics of these devices were measured before and after scanning and again after thermal annealing. The data includes transistor gain versus laser power; junction diode leakage current versus junction depth; MOSC-Vlifetime versus laser power and the effects of subsequent thermal anneals on all of these. The results are that bulk minority-carrier lifetime decreases of several orders of magnitude will be produced by either of these radiations at peak power levels below those which will produce any visible surface damage. The changes in minority-carrier lifetime are stable for post scanning thermal anneals up to 400°C and are almost completely removed from an 800°C anneal. The depths within which minority-carrier lifetime changes significantly are 0.7 and 1.8 µm for 0.53- and 1.06-µm wavelength laser radiations, respectively. The results indicate that the recombination centers produced by the scanning are point defects and their density decreases exponentially with the distance into the silicon. The average power thresholds for point defect production (for both 0.53- and 1.06-µm wavelengths) were determined and are observed to increase with increased laser wavelength and pulse width. Potential applications in silicon devices and integrated circuits such as selective lifetime doping, β trimming, and selective-link making without passivation damage are possible.     

激光模拟器衍射损耗的研究

半导体激光器给出的是半功率点处的发散角,在计算时必须进行变换,因实测LOC激光器发散角较大,本文对高斯光束发散角变换公式进行了少许修正,导出了模拟器衍射损耗公式,并计算了三种模拟器的衍射损耗。     

Simulation of vertical merged MOS elements with optical power supply

Functional optoelectronic vertical merged MOS (OVMMOS) elements with optical power supply increasing the packaging density for advanced high-speed low-voltage low-power deep-submicron ULSI are considered. Two types of new OVVMOS logical elements are proposed, analyzed and simulated. The simple reduced but adequate numerical electrical-optical model for the OVMMOS is formulated. Low-voltage low-power OVMMOS with combined channels for electrons and holes to increase integration level are simulated using two-dimensional (2D)-numerical device simulators. The problems of low light power operations and optimizations of OVMMOS elements are investigated using 2D simulators.