Three-Dimensional FinFET Source/Drain and Contact Design Optimization Study

The optimization of dopant-segregated Schottky (DSS) and raised source/drain (RSD) FinFETs is investigated through a 2-D and 3-D TCAD study. ldquoSilicide gatingrdquo due to fringing fields extending from a flared silicide contact degrades DSS and RSD FinFET performances. Thus, for a multifin DSS device, the individual source/drain fins should have minimal silicide flaring and be strapped with a metal bar. For large fin pitches (FPs), this results in lower intrinsic delay and much lower delay dependence on FP than optimized RSD FinFETs, which have source/drain fins strapped using lateral epitaxial growth and accessed with vias. However, RSD FinFETs achieve lower delay for small FP and fin heights (H _fin) due to low via-to-gate fringing capacitance. Thus, a new structure is proposed, called the recessed strap DSS FinFET, which combines the merits of optimized DSS and RSD FinFETs in a way that provides equivalent or improved performance over all ranges of FP and H _fin.     

Hot-carrier effects in P-channel modified Schottky-barrier FinFETs

High-performance p-channel modified Schottky-barrier SOI FinFETs (MSB pFinFETs) with low temperature source/drain annealing process was recently suggested for future nano-scale devices. In this letter, the hot-carrier (HC) immunity of the MSB pFinFETs with different gate lengths (L/sub g/) and fin widths (W/sub f/) are presented. The experimental data shows that the MSB pFinFET with narrower W/sub f/ has less hot carrier degradation than that with wider W/sub f/. The effects of electrical field in Si fins induced from lateral-gate electrode and the degree of uniformity of source/drain extension are illustrated cautiously by two-dimensional simulation and transmission electron microscopy (TEM) micrographs, respectively. It is found that the devices with narrower W/sub f/ have weaker electrical field from gate electrode and better uniformity of source/drain extension resulting in superior hot-carrier immunity. The projected operation voltage at ten years dc lifetime exceeds 1.6 V as the W/sub f/ is narrower than 60 nm. It is thus concluded that the MSB pFinFET would be a very promising nano device.     

Sub-60-nm quasi-planar FinFETs fabricated using a simplifiedprocess

N-channel double-gate metal-oxide-semiconductor field-effect transistor (MOSFET) FinFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process. Short channel effects are effectively suppressed when the Si fin width is less than two-thirds of the gate length. The drive current for typical devices is found to be above 500 μA/μm (or 1 mA/μm, depending on the definition of the width of the double-gate device) for V_g-V _t=V_d=1 V. The electrical gate oxide thickness in these devices is 21 Å, determined from the first FinFET capacitance-versus-voltage characteristics obtained to date. These results indicate that the FinFET is a promising structure for the future manufacturing of integrated circuits with sub-60-nm feature size, and that double-gate MOSFETs can meet international technology roadmap for semiconductors performance specifications without aggressive scaling of the gate-oxide thickness     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

FinFET器件总剂量效应研究进展

全面综述鳍式场效应晶体管(FinFET)的总剂量效应,包括辐照期间外加偏置、器件的工艺参数、提高器件驱动能力的特殊工艺、源/漏掺杂类型以及不同栅介质材料和新沟道材料与FinFET总剂量效应的关系。对于小尺寸器件,绝缘体上硅(SOI)FinFET比体硅FinFET具有更强的抗总剂量能力,更适合于高性能抗辐照的集成电路设计。此外,一些新的栅介质材料和一些新的沟道材料的引入,如HfO₂和Ge,可以进一步提高FinFET器件的抗总剂量能力。     

一种新型高性能FinFET的设计与特性分析

针对CMOS器件随着技术节点的不断减小而产生的短沟道效应和漏电流较大等问题,设计了一种新型直肠形鳍式场效应晶体管(FinFET),并将该新型器件与传统的矩形结构和梯形结构的FinFET通过Sentaurus TCAD仿真软件进行对比。结果表明,当栅极长度控制在10 nm时,新型器件相比于另外两种传统的FinFET具有更小的鳍片尺寸,且鳍片高度不低于抑制短沟道效应的临界值。仿真结果显示,这种新型的FinFET具有更好的开关特性和亚阈值特性。同时,该器件在射频方面的特性参数也显示出该器件具有较高性能,并有一定的实际应用价值。     

Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Using full 3D TCAD, an evaluation of process parameter space of bulk FinFET is presented from the point of view of DRAM, SRAM and I/O applications. Process and device simulations are performed with varying uniform fin doping, anti-punch implant dose and energy, fin width, fin height and gate oxide thickness. Bulk FinFET architecture with anti-punch implant is introduced beneath the channel region to reduce the punch-through and junction leakage. For 30 nm bulk FinFET, anti-punch implant with low energy of 15 to 25 keV and dose of 5.0 × 10¹³ to 1.0 × 10¹⁴ cm⁻² is beneficial to effectively suppress the punch-through leakage with reduced GIDL and short channel effects. Our simulations show that bulk FinFETs are approximately independent of back bias effect. With identical fin geometry, bulk FinFETs with anti-punch implant show same I_ON-I_OFF behavior and approximately equal short channel effects like SOI FinFETs.     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

Quantum mechanical analytical modeling of nanoscale DG FinFET: evaluation of potential,threshold voltage and source/drain resistance

Two-dimensional (2D) quantum mechanical analytical modeling has been presented in order to evaluate the 2D potential profile within the active area of FinFET structure. Various potential profiles such as surface, back to front gate and source to drain potential have been presented in order to appreciate the usefulness of the device for circuit simulation purposes. As we move from source end of the gate to the drain end of the gate, there is substantial increase in the potential at any point in the channel. This is attributed to the increased value of longitudinal electric field at the drain end on application of a drain to source voltage. Further, in this paper, the detailed study of threshold voltage and its variation with the process parameters are presented. A threshold voltage roll-off with fin thickness is observed for both theoretical and experimental results. The fin thickness is varied from 10 nm to 60 nm. The percentage roll-off for our model is 77% and that for experimental result it is 75%. Form the analysis of source/drain (S/D) resistance, it is observed that for a fixed fin width, as the channel length increases, there is an enhancement in the parasitic S/D resistance. This can be inferred from the fact that as the channel length decreases, quantum confinement along the S/D direction becomes more extensive. For our proposed devices a close match is obtained with the results through the analytical model and reported experimental results, thereby validating our proposed QM analytical model for DG FinFET device.     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.     

Sensitivity of double-gate and FinFETDevices to process variations

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.     

Strained p-Channel FinFETs With Extended Π -Shaped Silicon–Germanium Source and Drain Stressors

Further enhancement of performance in a strained p-channel multiple-gate or fin field-effect transistor (FinFET) device is demonstrated by utilizing an extended-Pi-shaped SiGe source/drain (S/D) stressor compared to that utilizing only Pi-shaped SiGe S/D. With the usage of a longer hydrofluoric acid cleaning time prior to the selective-epitaxy-raised S/D growth, a recess in the buried oxide is formed. This recess allows the subsequent SiGe growth on the fin sidewalls of the S/D regions to extend into the recessed buried oxide to provide a larger compressive stress in the channel for enhanced electrical performance compared to a device with SiGe S/D stressor. Process simulation shows that longitudinal compressive stress in the channel region is higher in a FinFET with extended-Pi-SiGe S/D than that with Pi-SiGe S/D. An enhancement of 26% in the drive current was experimentally observed, demonstrating further boost in enhancement of strained p-channel FinFET with little additional cost using this novel process.     

Characteristics of the full CMOS SRAM cell using body-tied TG MOSFETs (bulk FinFETs)

In this paper,the operational six-transistor SRAM cell characteristic was demonstrated using body-tied triple-gate MOSFETs (bulk FinFETs). A cell size of 0.79 /spl mu/m/sup 2/ was achieved with 90-nm node technology, using four levels of W and Al interconnects. A static noise margin of 280 mV was obtained at V/sub CC/ of 1.2 V by applying bulk FinFETs, and compared with those of typical optimized control devices and nanoscale planar channel MOSFETs. The characteristics of the bulk FinFETs were compared with those of nanoscale planar channel MOSFETs, and analyzed in detail by changing nanoscale active width (or fin width). Fabrication process issues for the bulk FinFETs were explained in terms of poly-Si gate over-etching and silicidation on nanoscale fin bodies. Also, input and output characteristics of the individual and parallel arrayed transistors were shown and analyzed.     

Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A_VO) and cutoff frequency (f_T ) of 25-nm gate-length FinFETs operated at low drain-current (I _ds=10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of A_VO (~45 dB) and f _T (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs     

Improving bulk FinFET DC performance in comparison to SOI FinFET

The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.     

Physical insights on electron mobility in contemporary FinFETs

Calibration of a physics/process-based model for double-gate (DG) MOSFETs to contemporary nanoscale undoped n-channel DG FinFETs reveals that 1) significant densities of source/drain donor dopants readily diffuse to the ultrathin (fin) body/channel, even with relatively long fin extensions, degrading electron mobility at low/moderate levels of inversion-carrier density (N/sub inv/), 2) surface-roughness scattering of electrons is less severe at the {110} silicon-fin surfaces than anticipated, and 3) strong-inversion electron mobility is quite high (e.g., /spl cong/290 cm/sup 2//V/spl middot/s at N/sub inv/=10/sup 13/ cm/sup -2/), being about three times higher than that in contemporary bulk-Si MOSFETs.     

Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate-dielectric thickness, the spacer width, fin width and pitch, as well as the gate height. For undoped fin with underlapping (nonoverlapping source/drain) gate, a thinner spacer with higher kappa value enhances the gate control of short-channel effects (SCEs) and reduces the source-to-drain leakage current. Our results also suggest that reducing the high- gate-dielectric thickness is no longer an effective approach to improve performance in small FinFET devices due to the strong fringing effect. However, the introduction of thin metal gate in a multifin device was found beneficial to device speed without compromising on current drive and SCE.     

亚20nm节点后栅工艺体硅FinFET器件参数优化研究

文章研究了亚 20nm 节点后栅工艺体硅 FinFET PMOS 器件制作过程中一系列工艺参数对器件微缩的影响。实验结果表明细且陡的梯形Fin结构有更好的性能。文章针对穿通阻挡层（PTSL） 和轻掺杂源漏扩散区 （SDE）的注入条件也进行了仔细地优化。SDE之后没有热退火过程的器件由于在源漏退火之后有更好的晶格再生因而拥有更大的驱动电流。带边功函数器件能够改善短沟道效应,而带中功函数具有更大的驱动电流。器件在微缩过程中针对金属栅的有效功函数需要折衷选择。     

A study of negative-bias temperature instability of SOI and body-tied FinFETs

Negative-bias temperature-instability (NBTI) characteristics are carefully studied on SOI and body-tied pMOS FinFETs for the first time. It was observed that a narrow fin width degraded device lifetime more than a wider fin width. Electrons generated by the NBT stress are accumulated at the center of a silicon fin and cause energy-band bending. This results in an incremental hole population at the interface. The energy band is bent more steeply at the narrow fin than at the wide fin by the accumulated electrons. A body-tied FinFET shows better immunity to NBT stress due to a substrate contact.     

Fin Width $(W_{rm fin})$ Dependence of Programming Characteristics on a Dopant-Segregated Schottky-Barrier (DSSB) FinFET SONOS Device for a NOR-Type Flash Memory Device

This letter is aimed at experimentally investigating the fin width (W_fin) dependence of both a dopant-segregated Schottky-barrier (DSSB) and a conventional FinFET SONOS device with diffused p-n junctions for application of a NOR-type flash memory device. High parasitic resistance (R_para) at the source/drain by a narrowed W_fin results in degradation of memory performance for the conventional FinFET SONOS device. In contrast, it is shown that a narrow W_fin significantly improves the memory performance for the DSSB FinFET SONOS device, resulting from an improved lateral electric field without a significant change of the R_para value.