共查询到20条相似文献,搜索用时 218 毫秒
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针对车牌识别系统的车牌精确定位和车牌字符准确识别问题。提出一种基于SVM(支持向量机)和BP神经网络的车牌定位与识别算法。通过将HSV颜色空间和形态学方法相结合确定候选轮廓,以判断轮廓外接矩形的面积和长宽比筛选符合车牌特征的区域,并利用训练好的SVM模型对候选车牌区域进行测试判断,最终精确定位车牌的位置。此外,还可使用了BP神经网络进行车牌字符识别。经验证,该系统适用于复杂的车牌定位环境,且识别速度快,准确率高。 相似文献
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徐桦 《电信工程技术与标准化》2016,(10)
要进行LTE网络的精细优化必须依赖于对覆盖和干扰的地理分布精确掌握。本文基于MR数据建立精确定位干扰矩阵,形成从覆盖、干扰、用户、空间、时间等多维度定位网络问题的MR分析方法。 基于模式识别理论和MR数据的精确定位分析,智能识别出覆盖和干扰的场景,针对这些问题场景通过迭代算法自动生成相应的优化策略。 相似文献
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基于OpenCV的石英晶片污垢检测技术研究 总被引:1,自引:1,他引:0
污垢检测是石英晶片缺陷检测的重要组成部分。为实现比较理想的污垢检测,采用基于开源计算机视觉库OpenCV的图像处理技术对石英晶片污垢缺陷进行检测。在此通过依次对图像进行平滑去噪、二值化阈值分割、轮廓提取和跟踪等处理,计算出轮廓的周长,将有缺陷与无缺陷晶片轮廓进行比较,为晶片污垢检测提供依据。实验结果表明在VisualStudio2008环境下,利用OpenCV库函数缩短了大量编程时间,提高了工作效率。 相似文献
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阐述一种新型的硅片自动定位方法,并介绍了其特点和具体的实现方法。此方法可适应不同规格晶片的定位要求,实用性强。 相似文献
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利用加热装置对晶片样片进行加热,采用机器视觉定位系统对晶片进行拍照采样,并利用图像处理软件进行位置识别,分析了在加热对图像定位系统的影响,并采取了措施降低热气流的影响,取得了比较满意的结果. 相似文献
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压电振子作为压电驱动机构的核心部件,其工作状态和疲劳强度直接决定系统的工作性能和使用寿命。该文利用ANSYS软件对圆环形压电振子进行疲劳仿真分析,得到振动模态云图和最大受力点。研究不同结构尺寸参数对压电振子疲劳寿命影响,并进行双晶片与单晶片压电振子相关数据对比。结果表明,金属材料65Mn的抗疲劳性能最好,减小振子直径或增加振子厚度能较好提高其疲劳寿命,而施加电压幅值过高会降低振子的使用寿命,双晶片压电振子的疲劳寿命比单晶片压电振子疲劳寿命长。对圆环形压电振子进行了疲劳寿命实验,研究表明,选取的此批振子完全能达到使用要求。 相似文献
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Advanced technologies of microelectronic device fabrication need accurate determination of process parameters and their analysis. Test structures which represent individual process steps are incorporated in the design. Independent measurements can be carried out on these structures and the information is used as a feedback in order to achieve perfection at different stages of fabrication. This note presents an algorithm for analysis of measurement data and identification of defective sites on the wafer leading to an accurate yield analysis. 相似文献
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月球轨道器激光高度计(Lunar Orbiter Laser Altimeter, LOLA)是目前月球探测中获取数据量最大、精度最高的激光高度计,可为其他月球产品提供地理控制。然而由于定轨不确定性和激光指向偏差,部分激光剖面存在地理定位误差。针对这些异常轨道数据,提出了一种改进的激光自约束调整方法。首先基于坡度将与周围地形差异过大的激光剖面识别为异常轨,并使用其余轨道作为参考对其进行基于点密度的自约束轨道调整(根据参考点密度自动选取合适的调整策略),最后合并两类轨道数据并进行最终调整,再将其作为改正后的结果。交叉点分析结果表明,该方法能有效校正异常轨道,从而提升数据精度。 相似文献
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Results are presented of comparative reliability testing of multichip modules (MCM's) fabricated with laminate substrates, and protected with various bare-die coatings. The demonstration MCM's included two design versions (flip-chip and wire-bond) of the digital portion of global positioning system (GPS) receiver multichip modules. This paper summarizes the results for the wire-bonded constructions. Standard encapsulants and new inorganic coatings (Dow Coming's ChipSeal(R) hermetic coating materials') were evaluated in environmental stress exposures corresponding to high reliability avionics applications. Full wafer probe testing was performed both before and after the supplemental ChipSeal processing and dip-chip wafer bump processing steps. ChipSeal and flip-chip wafer processing steps were shown to cause no yield degradation on wafer lots of five different IC types used in the overall program. The environmental test results demonstrate that MCM-L units with bare die packaging can be designed for very robust reliability applications such as military and other high reliability avionics 相似文献
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In this work, a new feature-scale model is proposed for investigating the interaction between the wafer pattern and individual pad asperities in the process of chemical mechanical planarization (CMP). Based on the contact mechanics equation and the modified Greenwood–Williamson (GW) model which captures the evolution of feature curvature and the modification of the pad asperity height distribution, the discrete convolution and fast Fourier transform (DC-FFT) technique is adopted and combined with the Picard iteration method to calculate the direct contact pressure distribution between the wafer surface and the polishing pad. The computed pressure is then used to determine the local removal rate of the underlying patterns and predict the evolution of the wafer surface profile. Furthermore, the method is extended to capture the metal dishing as the feature size changes. It is shown that the present model can avoid the false simulated results produced by directly applying the original GW model for CMP when the feature size approaches zero. Otherwise, the calculated surface profile and dishing values of pattern geometries are in good agreement with the experimental data. Therefore, this model can not only be used to simulate the evolution of the wafer surface for global planarization at lower technology nodes, but can also be applied to provide some basic design rules for improving the process parameters and reducing the time and cost for developing new architectures. 相似文献
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M. Despont U. Staufer C. Stebler H. Gross P. Vettiger 《Microelectronic Engineering》1996,30(1-4):69-72
In this paper, we report the improvement of a process for full microfabrication of miniaturized electron lenses specially design for low-energy (100 eV) lithography tools. The main advantages of this technique are the following. It is batch processing oriented, meaning that lenses can be easily built in a full wafer fabrication. With this procedure it is possible to develop a completely integrated process for machining arrays of lenses. Lens bores are aligned using an electron lithography process, resulting in highly accurate positioning. Finally, the source lens chip has not only one but several sets of lenses with different aperture-sizes, each producing a different beam diameter. A scheme is proposed with which the appropriate lens can be selected by means of a deflection system. 相似文献
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Fei-Long Chen Shu-Fan Liu 《Semiconductor Manufacturing, IEEE Transactions on》2000,13(3):366-373
Yield enhancement in semiconductor fabrication is important. Even though IC yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form spatial patterns, it is usually a clue for the identification of equipment problems or process variations. This research intends to develop an intelligent system, which will recognize defect spatial patterns to aid in the diagnosis of failure causes. The neural-network architecture named adaptive resonance theory network 1 (ART1) was adopted for this purpose. Actual data obtained from a semiconductor manufacturing company in Taiwan were used in experiments with the proposed system. Comparison between ART1 and another unsupervised neural network, self-organizing map (SOM), was also conducted. The results show that ART1 architecture can recognize the similar defect spatial patterns more easily and correctly 相似文献
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Gyurcsik R.S. Riley T.J. Sorrell F.Y. 《Semiconductor Manufacturing, IEEE Transactions on》1991,4(1):9-13
A first-principles approach to the modeling of a rapid thermal processing (RTP) system to obtain temperature uniformity is described. RTP systems are single wafer and typically have a bank of heating lamps which can be individually controlled. Temperature uniformity across a wafer is difficult to obtain in RTP systems. A temperature gradient exists outward from the center of the wafer due to cooling for a uniform heat flux density on the surface of the wafer from the lamps. Experiments have shown that the nonuniform temperature of a wafer in an RTP system can be counteracted by adjusting the relative power of the individual lamps, which alters the heat flux density at the wafer. The model is composed of two components. The first predicts a wafer's temperature profile given the individual lamp powers. The second determines the relative lamp power necessary to achieve uniform temperature everywhere but at the outermost edge of the wafer (cooling at the edge is always present). The model has been verified experimentally by rapid thermal chemical vapor deposition of polycrystalline silicon with a prototype LEISK RTP system. The wafer temperature profile is inferred from the poly-Si thickness. Results showed a temperature uniformity of ±1%, an average absolute temperature variation of 5.5°C, and a worst-case absolute temperature variation of 6.5°C for several wafers processed at different temperatures 相似文献
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Skinner K.R. Montgomery D.C. Runger G.C. Fowler J.W. McCarville D.R. Rhoads T.R. Stanley J.D. 《Semiconductor Manufacturing, IEEE Transactions on》2002,15(4):523-530
Probe testing following wafer fabrication can produce extremely large amounts of data, which is often used to inspect a final product to determine if the product meets specifications. This data can be further utilized in studying the effects of the wafer fabrication process on the quality or yield of the wafers. Relationships among the parameters may provide valuable process information that can improve future production. This paper compares many methods of using the probe test data to determine the cause of low yield wafers. The methods discussed include two classes of traditional multivariate statistical methods, clustering and principal component methods and regression-based methods. These traditional methods are compared to a classification and regression tree (CART) method. The results for each method are presented. CART adequately fits the data and provides a "recipe" for avoiding low yield wafers and because CART is distribution-free there are no assumptions about the distributional properties of the data. CART is strongly recommended for analyzing wafer probe data. 相似文献