Cost-effective chip-on-heat sink leadframe package for 800-Mb/s/lead applications

Chip-on-heat sink leadframe (COHS-LF) packages offer a simple, low-cost chip encapsulation structure with advanced electrical and thermal performance for high-speed integrated circuit applications. The COHS-LF package is a novel solution to the problems of increased power consumption and signal bandwidth demands that result from high-speed data transmission rates. Not only does it offer high thermal and electrical performance, but also provides a low-cost short time-to-market package solution for high-speed applications. In general, there are two main memory packages employed by the most popular high-speed applications, double data rate (DDR) SDRAM. One is the cheaper, higher parasitic leadframe packages, such as the thin small outline packages (TSOPs), and the other is the more expensive, lower parasitic substrate-based packages, such as the ball grid array (BGA). Due to the requirement for higher ambient temperature and operating frequency for high-speed devices, DDR2 SDRAM packages were switched from conventional TSOPs to more expensive chip-scale packages (i.e., BGA) with lower parasitic effects. And yet, by using an exposed heat sink pasted on the surface of the chip and packed in a conventional leadframe package, the COHS-LF is a simpler, lower cost design. Results of a three-dimensional full-wave electromagnetic field solver and SPICE simulator tests show that the COHS-LF package achieves less signal loss, propagation delay, edge rate degradation, and crosstalk than the BGA package. Furthermore, transient analysis using the wideband T-3/spl pi/ models optimized up to 5.6 GHz for signal speeds as high as 800 Mb/s/lead demonstrates the accuracy of the equivalent circuit model and reconfirms the superior electrical characteristics of COHS-LF package.     

Frequency Characteristics of New Ceramic Stem-Based TO Package Using a Coplanar Waveguide Feed-Line for 10-Gb/s Data Transmissions

A ceramic stem-based transistor outline (TO) package, incorporating a coplanar waveguide (CPW) feed-line, has been proposed allowing 10-Gb/s grade data transmissions. Initially, the frequency response of a cylindrical feed-line for a conventional metal-based TO package was analyzed. It was compared to that of the coplanar waveguide feed-line used for a ceramic-based module, such as butterfly packages. For a laser diode (LD) module-based on an LD chip, the measured 3-dB frequency bandwidths were 3.5 and 7.8 GHz for the conventional and proposed packages, respectively. The results validate theoretical results obtained from modeling a small signal equivalent circuit. Based on these results, it has been proposed a new ceramic-based TO package with a CPW feed-line in ceramic material to improve the frequency characteristics of the TO package. The performance of the proposed package was theoretically observed. It was confirmed that it provides wider frequency bandwidth, compared to the conventional one.      

X波段T/R组件功率放大器芯片的热设计

针对X波段T/R组件中的功率放大器芯片,建立芯片热模型,给出了获取器件热阻的公式和方法,并对功放芯片的等效热路进行了分析计算.文中给出了常用材料的热导率,对不同壳底材料,求出了在确保功放可靠工作下的系统最大热沉温度,从而为组件设计师优化组件成本提供了依据.最后提出了提高功率芯片可靠性的建议.     

Microwave Equivalent-Circuit Parameters of Gunn-Effect-Device Packages

The packages in which Gunn-effect devices are commonly mounted are found to have parasitic reactances which are significant at X-band. An accurate knowledge of the package equivalent circuit is essential. Precision measurements in a coaxial system have therefore been made over a very wide range of frequencies, and a consistent equivalent circuit has been derived. This differs somewhat from previously assumed equivalent circuits. The experimental results are analyzed in terms of a theoretical model based on the known structure of the package.     

Electrical performance improvements on RFICs using bump chipcarrier packages as compared to standard thin shrink small outlinepackages

The electrical models of bump chip carrier (BCC) packages have been established based on the S-parameter measurement. When compared to the standard thin shrink small outline packages (TSSOPs), BCC packages show much smaller parasitics in the equivalent model. In the simulation, the insertion and return losses for a packaged 50-Ω microstrip line are calculated against frequency. BCC packages are also less lossy than TSSOPs over a wide frequency range. By setting a random variable with Gaussian distribution varied within a certain range for each equivalent circuit element of the packages, the Monte Carlo analysis has been performed to study the package effects on a GaAs heterojunction bipolar transistor (HBT). Again, BCC packages cause less decrement of HBT unity-gain bandwidth than TSSOPs     

Equivalent circuit of a dipole antenna using frequency-independentlumped elements

A four-element lumped-parameter equivalent circuit, consisting of a resistance, an inductance, and two capacitances, has been found to represent the feed-point impedance of a dipole antenna. The values of these elements are related only to the physical dimensions of the antenna, not the frequency of operation. Empirical formulas are given for all the elements. The equivalent circuit gives negligible errors in radiation resistance and reactance for dipole half-lengths less than 0.1λ, rising to 1% for resistance and 6% for reactance at 0.25λ. It can be readily used in standard computer software packages such as SPICE, PSPICE, and MICROCAP     

A physics-based dynamic thermal impedance model for verticalbipolar transistors on SOI substrates

A physics-based compact model for the thermal impedance of vertical bipolar transistors, fabricated with full dielectric isolation, is presented. The model compares favorably to both three dimensional (3-D) ANSYS(R) transient simulations and measurements. Using the software package Thermal Impedance Pre-Processor (TIPP), a multiple-pole circuit can be fitted to the thermal impedance model. The thermal equivalent circuit is used in conjunction with a modified version of SPICE to give efficient electrothermal simulations in the dc and transient regimes     

Projected life-times of circuits in Krypton85contaminated packages

This article presents a Monte Carlo model which calculates the radiation dose absorbed by the oxide layers on the chip from the radioactivity level in a package. The simulation allows one to obtain the time of failure of a given circuit, based on the initial activity in the package and the radiation hardness of the circuit. The model includes the effects of β-particle energy spectrum, package geometry, electron backscattering, and beta absorption through layers of various materials on the chip. Our simulation shows that the levels of Kr⁸⁵contamination assumed to be harmless in the literature may in fact cause long term failures in some memories in typical hermetically-sealed ceramic packages.     

A Semi-Analytical Approach for System-Level Electrical Modeling of Electronic Packages With Large Number of Vias

This paper presents a semi-analytical approach for electrical performance modeling of complex electronic packages with multiple power/ground planes and large number of vias. The method is based on the modal expansion technique and the method of moments. For the inner package domain with multiple power/ground planes and many vias, the modal expansion method is employed to compute the electromagnetic fields from which the multiport network parameters, e.g., the admittance matrix can be easily obtained. For the top/bottom domain of signal layers, the moment method is used to extract the equivalent resistance, inductance, capacitance, and conductance (RLCG) parameters. The equivalent circuit for the entire package is then generated by combining the results for both package domains. The equivalent circuit can be used in a SPICE-like simulator to study the signal and power integrity of an electronic package. Numerical examples demonstrate that the new approach is able to provide fast yet accurate signal and power integrity analysis of multilayered electronic packages.     

Mount-independent equivalent circuit of the S4 diode package

Broadband-admittance measurements have been made on dummy S4 diode packages mounted in a coaxial line. By comparing these with the theoretical admittance of a lumped-component equivalent circuit for the package and its mount similar to that of Getsinger, a consistent set of mount-independent equivalent-circuit parameters for the package has been derived.     

Open‐Ended Two‐Strip Meander‐Line Antenna for RFID Tags

A new meander‐line antenna consisting of two open‐ended strips is proposed for a compact and broadband UHF radio frequency identification tag. An equivalent circuit model for the proposed antenna is derived and used to perform a simple and wideband impedance match to an arbitrary complex impedance of a tag chip without any additional matching network. The performance of the proposed antenna is validated by comparing calculated and measured results, which show good agreement.     

The effects of underfill and its material models onthermomechanical behaviors of a flip chip package

In this paper, the effects of underfill on thermomechanical behavior of two types of flip chip packages with different bumping size and stand-off height were investigated under thermal cycling both experimentally and two-dimensional (2-D) finite element simulation. The materials inelasticity, i.e., viscoelasticity of underfill U8437-3 and viscoplasticity of 60 Sn40 Pb solder, were considered in the simulations. The results show that the use of underfill encapsulant increases tremendously (~20 times) the thermal fatigue lifetime of SnPb solder joint, weakens the effects of stand-off height on the reliability, and changes the deformation mode of the package. It was found that the thermal fatigue crack occurs in the region with maximum plastic strain range, and the Coffin-Manson type equation could then be used for both packages with and without underfill. Solder joint crack initiation occurred before delamination when using underfill with good adhesion (75 MPa) and the underfill delamination may not be a dominant failure mode in the present study. The interfacial stresses at the underfill/chip interface were calculated to analyze delamination sites, which agree with the results from acoustic image. Moreover, the effects of material models of underfill, i.e., constant elasticity (EC) and temperature dependent elasticity (ET) as well as the viscoelasticity (VE), on the thermomechanical behaviors of flip chip package were also studied in the simulation. The VE model gives comparatively large plastic strain range and large displacements in the shear direction, as well as decreased solders joint lifetime. The ET model gives similar results as the VE model and could be used instead of VE in simulations for the purpose of simplicity     

多层芯片堆叠封装方案的优化方法

芯片堆叠封装是提高存储卡类产品存储容量的主流技术之一,采用不同的芯片堆叠方案,可能会产生不同的堆叠效果.针对三种芯片堆叠的初始设计方案进行了分析,指出了堆叠方案失败的原因和不足.结合两种典型芯片堆叠封装结构(金字塔型和悬梁式)的特点,提出了一种采用转接芯片完成焊盘转移的优化方法,并举例进行了芯片堆叠封装方案的说明.最后,对转接芯片的制作及尺寸设计原则进行了研究.     

Modeling of power distribution systems for high-performancemicroprocessors

This paper presents approximate techniques for building models and simulating the response of power distribution systems for high-performance microprocessors. Several distributed equivalent SPICE circuit models were built by extracting the appropriate resistance, inductance, capacitance (RLC) component values using a combination of two-dimensional (2-D) and three-dimensional (3-D) quasi-static field solvers. They were used to assess how well such effects as system transfer impedance and transient characteristics can be predicted. The models include the chip, its controlled collapsed chip connection (C4) connections to the package, the power distribution structure in the package, connector and motherboard. It is found that the response of the entire power system can be treated as a second order system, by which the main features of the performance of the power delivery network are assessed. Samples of transient and frequency domain data for typical microprocessors are given and the effects of some design options are discussed, as are the tradeoffs in model complexity versus the gain of useful design information     

Small signal equivalent circuit modeling of resonant converters

A general analytical procedure is presented for the equivalent circuit modeling of resonant converters, using the series and parallel resonant converters as examples. The switched tank elements of a resonant converter are modeled by a lumped parameter equivalent circuit. The tank element circuit model consists, in general, of discrete energy states, but may be approximated by a low-frequency continuous time model. These equivalent circuit models completely characterize the terminal behavior of the converters and are solvable for any transfer function or impedance of interest. With the approximate model it is possible to predict the lumped parameter poles and zeros, and to quickly determine the relevant DC gains of the output impedance and the control to output transfer function. Closed-form solutions are given for the equivalent circuit models of both converter examples. Experimental verification is presented for the control-to-output transfer functions of both series and parallel resonant converters, and good agreement between theoretical prediction and experimental measurement is obtained     

Reliable prediction of EM radiation from a PCB at the design stageof electronic equipment

This paper presents a composite computer-aided design (CCAD) package for prediction of electromagnetic (EM) radiation from a printed circuit board (PCB) at the design stage of equipment. Such a CCAD package has been developed by combining an EM computation tool such as numerical electromagnetic code (NEC)-2, with other circuit design packages (CDPs). The method of prediction of EM radiation using the CCAD is well described in this paper. The predicted EM radiation has been validated experimentally and results showing good agreement are presented. Finally, the reliability of the CCAD package is investigated and presented     

Complete methodology for electrical modeling of RFIC packages

A complete methodology based on broadband S-parameter measurement is proposed to establish the electrical models for radio-frequency integrated circuit (RFIC) packages. The research is focused on calibration of the test-fixture parasitics to obtain the intrinsic S-parameters from which an equivalent coupled lumped model can be extracted for any pair of package leads under test. Then a step-by-step optimization scheme is employed to construct an equivalent circuit for the whole package. A real example on modeling a 16-lead Thin Shrink Small Outline Package (TSSOP) has been demonstrated. The established model can account for various package effects at radio frequencies     

Design of high-efficiency RF Class-D power amplifier

In this paper, the losses in a Class-D RF switching power amplifier and their frequency dependence are described. The losses analyzed are the switching, conduction, and gate drive losses. A 300 W, 13.56 MHz, Class-D circuit is designed in the traditional manner to illustrate the magnitude of the different types of loss. A circuit using the ZVS equations developed in this paper is designed. An experimental circuit is built using standard IRF540 devices in TO220 packages. That circuit does not meet its performance goals because of the package inductance. A new low inductance half-bridge package is introduced to solve this problem. Techniques for circuit layout and power measurements for RF applications are also presented in the experimental section. A low loss gate drive circuit is also presented using a Class-E circuit to provide the drive power. The experimental results confirm the accuracy of the design equations derived in this paper