Offset-compensated switched-capacitor circuits

Novel switched-capacitor circuits are described which make the offset-compensation possible without short-circuiting the input and output terminals of op amps. Based on a common configuration, the proposed circuits are useful for basic building blocks integrable using the semicustom IC process.     

A high-slew integrator for switched-capacitor circuits

A new method for improving the slew rate of a switched-capacitor integrator is introduced. A booster circuit is used to measure the integrator input voltage and then inject a proportionate amount of charge at the integrator output. The boosted integrator significantly reduces the settling time due to amplifier slewing. In addition, the booster has no adverse effect on the noise and stability performance of the integrator. The booster stage increases the total static integrator power by 36% and the total die area by 22%     

GaAs switched-capacitor circuits for high-speed signal processing

Switched-capacitor building blocks are presented which are suitable for implementation in GaAs MESFET technology. They include gain stages, operational amplifiers, and transmission gates. Switched-capacitor design techniques are discussed that minimize filter sensitivity to GaAs op-amp limitations. Experimental results are presented on a variety of GaAs switched-capacitor circuits, including a gain stage, a second-order bandpass filter, and a third-order low-pass filter. The circuits demonstrate sampling rates exceeding 100 MHz without significant loss of accuracy.     

RFI-induced distortion in switched-capacitor circuits

The errors which are induced by radio-frequency interference (RFI) in switched-capacitor (SC) circuits are discussed and the main role played by the distortion of MOS switches in the on-state is highlighted. Furthermore, a new simple analytical model, which enables one to predict RFI-induced errors in SC circuits is proposed and it is validated by the comparison of its predictions with time-domain computer simulation results.     

Floating integrator technique for switched-capacitor circuits employing reset cycles

A simple `floating? integrator technique is presented that is applicable to both single-ended and differential switched-capacitor circuits which employ reset cycles. This method is useful in eliminating the effects of any input offset or interstage differential or common-mode offsets in DC-coupled circuits. A monolithic circuit is demonstrated which uses this technique to achieve accurate differential integration of low-level signals in the presence of substantial differential and common-mode input offsets.     

Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits

In this paper, a time-domain design procedure for fast-settling three-stage amplifiers is presented. In the proposed design approach, the amplifier is designed to settle within a specific time with a given settling accuracy and circuit noise budget by optimizing both the power consumption and silicon die area. Both linear and nonlinear settling regions of three-stage amplifiers are considered and optimal values of the amplifier stages transconductance and compensation capacitors are obtained using the genetic algorithm optimization. Detailed design equations are provided and circuit level simulation results using a 90 nm CMOS technology are presented to evaluate the usefulness of the proposed design scheme respected to the previously reported design approaches.     

Design for testability and DC test of switched-capacitor circuits

The authors present a design for testability (DFT) technique for switched-capacitor circuits. The principle is to reconfigure the SC circuit so that it realises a cascade of DC voltage amplifiers in which all capacitors are represented in a simple form. Then, the transfer function becomes a product of the ratio of two capacitors and the sensibility of the DC gain to each capacitor is close to unity. Consequently, a simple test with partial diagnosis is realised with some DC voltage stimuli and gives an accurate test result at the output of the last voltage amplifier     

Simple method for obtaining the equations of switched-capacitor circuits

A systematic method for writing the time-domain equations of switched-capacitor circuits is presented. By following four well-defined steps, as many linearly independent equations are obtained as there are capacitors in the circuit. The method is especially well suited for hand analysis, and relies on the intuitively appealing concept of identifying physical regions where charge is trapped.     

Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2-/spl mu/m CMOS technology. The first one is a fully differential SC bandpass biquad working at 1.5 V and 5.0-MHz clock frequency. The measured Q value is 8.0 at the center frequency of 833 kHz. The second one is a fully differential fourth-order bandpass /spl Delta//spl Sigma/ modulator that also works at 1.5 V and 5.0 MHz. Its measured third-order intermodulation is less than -78 dBc due to the low distortion characteristic of AZI. The measured signal-to-noise ratio of the modulator is 61 dB within the narrow band of 25 kHz centered at 1.25 MHz.     

Chaos from switched-capacitor circuits: Discrete maps

A special-purpose analog computer made of switched-capacitor circuits is presented for analyzing chaos and bifurcation phenomena in nonlinear discrete dynamical systems modeled by discrete maps xn + 1= f(xn) Experimental results are given for four switched-capacitor circuits described by well-known discrete maps; namely, the logistic map, the piecewise-linear unimodal (one-hump) map, the Hénon map, and the Lozi map.     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

Improved circuit elements for switched-capacitor ladder filters

A new switched-capacitor floating inductance simulation circuit which does not depend on matching of passive elements is presented. A switched-capacitor source termination circuit which functions as a sample-and-hold circuit for a filter is also described.     

Improved switched-capacitor algorithmic analogue-to-digital convertor

A novel switched-capacitor circuit is presented for algorithmic analogue-to-digital conversion. Besides the reduced component count, the proposed circuit shows that it can accept a differential analogue signal. A conversion accuracy higher than 12 bits is easily attainable with its integrated version.     

A tutorial on computer-aided analysis of switched-capacitor circuits

In this paper, various formulation techniques for analyzing switched-capacitor circuits have been described and compared. Some basic pcoperties of the time-, z-, and frequency-domain solutions have been presented. Analysis techniques for handling nonideal op-amps, switch resistances, and noise and distortion effects are discussed. Methods for sensitivity analysis have been briefly mentioned and, finally, an overview of computer-aided analysis techniques has been given.     

Improved circuit for switched-capacitor simulation of an inductor

A new circuit for the switched-capacitor realisation of a lossless inductance, which is based on the bilinear transformation, is described. It requires only a grounded-input grounded-output operational amplifier and three capacitors.