双掺硅P-N结特性

双掺硅单晶片经热氧化后在其表面能够形成浅而均匀的P-N结.本文研究这类P-N结的基本特性,在耗尽层近似下给出P-N结空间电荷区中电场分布和电势的解析表达式,并讨论分析P-N结的光电特点.研究结果说明:双掺硅P-N结很有可能应用于光电器件、太阳能电池、集成电路和某些特殊器件.     

双掺硅单晶基本物理特性的研究

按一定掺杂比例制备了一种双掺硅单晶.单晶片经热处理后形成的P-N结具有结深浅、均匀、杂质浓度分布不同于扩散结和离子注入结等特点.本文研究了这种双掺硅单晶的基本物理特性;测量了各种电学参数和进行了位错等晶体缺陷的金相观察,并将这种材料与单掺杂硅单晶的某些电学性质进行了比较.     

双掺硅单晶及其P-N结研究

<正>按照一定的掺杂比例制备了一种双掺硅单晶.单晶片经热氧化或惰性气体中热处理,可以在其表面获得P-N结.这种P-N结具有下述特点:(1)可重复地得到大面积、均匀的浅结,P-N结结深最浅可以控制在0.1微米以下,甚至百埃(?)数量级.(2)表面是n型低浓度区,体内是P型高浓度,与扩散结、离子注入结和合金结的浓度分布不同.     

高耐压平面工艺简介

一、前言平面工艺在半导体硅器件的制造中是一项特别重要的技术,它在小功率晶体管、闸流管和集成电路等方面得到了广泛的应用。平面器件的一个特点是,其P-N结的曝露部分都用硅的氧化膜(二氧化硅)等无机绝缘膜加以复盖,所以可靠性较好。另一个特点是,几乎每个工艺都能成批地做片子,并可以用价钱便宜的塑料等进行封装,因此,制造成本较低。     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法.这种方法是直接在硅衬底形成间隔的pn结隔离以阻止螺旋电感诱导的涡流.衬底pn结间隔能用标准硅工艺实现而不需另外的工艺.本文设计和制作了硅集成电路,测量了硅集成电感的S参数并且从测量数据提取了电感的参数.研究了衬底结隔离对硅集成电感的品质因素Q的影响.结果表明一定深度的衬底结隔离能够取得很好的效果.在3GHz,衬底pn结隔离能使电感的品质因素Q值提高40%.     

新颖的衬底pn结隔离型硅射频集成电感

提出了一种新的减小硅集成电感衬底损耗的方法 .这种方法是直接在硅衬底形成间隔的 pn结隔离以阻止螺旋电感诱导的涡流 .衬底 pn结间隔能用标准硅工艺实现而不需另外的工艺 .本文设计和制作了硅集成电路 ,测量了硅集成电感的 S参数并且从测量数据提取了电感的参数 .研究了衬底结隔离对硅集成电感的品质因素 Q的影响 .结果表明一定深度的衬底结隔离能够取得很好的效果 .在 3GHz,衬底 pn结隔离能使电感的品质因素 Q值提高4 0 % .     

激光束感应电流法研究HgCdTe电活性缺陷和焦平面器件的光电特性

用高分辨率的、非破坏的光学表征技术的激光束感应电流研究碲镉汞(MCT)晶片中电活性缺陷和光伏型红外碲镉汞焦平面器件及光伏型硅光电器件P-N结光电特性,实验表明在MCT晶片中探测到激光束感应电流,在光伏型P-N结构的器件中,观察到周期结构的激光束感应电流分布.定性地观察激光束感应电流图谱以及定量地分析单个P-N结的感应电流分布形状可以判断器件的均匀性和器件的质量.     

外延迁移技术制作用于光电子单片集成的Si上GaAs／GaAlAsDHLED

描述了在国内首次采用外延迁移技术研制适合于制作光电子集成电路的硅上硬化镓双异质结发光二极管的工艺过程及实验结果。发光器件是在外延迁移以后流片制作的，克服了光子器件的对准问题，可与电子器件大规模集成。     

绝缘栅场效应晶体管集成电路工艺和特性

本文叙述了利用多晶硅做栅电极的绝缘栅场效应晶体管集成电路的工艺和特性。在概述硅栅工艺特性之后,还评述了硅-二氧化硅-硅系统的某些基本特性,制造硅栅器件的工艺步骤,以及所制得器件的电特性。利用具有译码逻辑电路的八个通道的3705型多重开关对硅栅工艺与一般工艺进行比较。给出了硅栅工艺的设计考虑和某些设计样品。     

硅基发光材料和器件研究的进展

发光器件和集成电路都是信息技术的基础。如果能将它们集成在一个芯片上,信息传输速度,储存和处理能力将得到大大提高,它将使信息技术发展到一个全新的阶段,但是,现在的集成电路是采用硅材料,而发光器件则用ｉｌｌ－Ｖ族化合物半导体。Ｉｌｌ－Ｖ族化合物半导体集成电路,虽然经过多年的研制,但至今还不成熟。因此,研究硅基发光材料和器件成为发展光电子集成的关键。本文评述了目前取得较大进展的几种主要硅基发光材料和器件的研究,包括掺铒硅、多孔硅、纳米硅以及 Ｓｉ／ＳｉＯ_２等超晶格结构材料,并展望了这些不同硅基发光材料和发光器件在光电集成中的发展前景。     

全色波段硅双结型色敏器件的研制

通过理论分析得出硅双结型色敏器件中掺杂浓度和两个结的结深是影响光谱响应范围的主要因素。通过选择不同的器件结构和工艺条件，得到了色敏器件对蓝紫光的响应，完成了金色波段硅双结型色敏器件的研制。     

电化学电容-电压法表征等离子体掺杂超浅结

采用电化学电容-电压(ECV)法对等离子体掺杂制备的Si超浅p n结进行了电学表征.通过对超浅p n结样品ECV测试和二次离子质谱(SIMS)测试及比较,发现用ECV测试获得的p 层杂质浓度分布及结深与SIMS测试结果具有良好的一致性,但ECV测试下层轻掺杂n型衬底杂质浓度受上层高浓度掺杂影响很大.ECV测试具有良好的可控性与重复性.对不同退火方法等离子体掺杂形成的超浅结样品的ECV系列测试结果表明,ECV能可靠地表征结深达10nm,杂质浓度达1021cm-3量级的Si超浅结样品,其深度分辨率可达纳米量级,它有望在亚65nm节点CMOS器件的超浅结表征中获得应用.     

Direct Laser Patterning of a 2D WSe2 Logic Circuit

Carrier doping is the basis of the modern semiconductor industry. Great efforts are put into the control of carrier doping for 2D semiconductors, especially the layered transition metal dichalcogenides. Here, the direct laser patterning of WSe₂ devices via light-induced hole doping is systematically studied. By changing the laser power, scan speed, and the number of irradiation times, different levels of hole doping can be achieved in the pristine electron-transport-dominated WSe₂, without obvious sample thinning. Scanning transmission electron microscopy characterization reveals that the oxidation of the laser-radiated WSe₂ is the origin of the carrier doping. Photocurrent mapping shows that after the same amount of laser irradiation, with increasing thickness, the laser patterned PN junction changes from the pure lateral to the vertical-lateral hybrid structure, accompanied by the decrease in the open circuit voltage. The vertical-lateral hybrid PN junction can be tuned to a pure lateral one by further irradiation, showing possibilities to construct complex junction profiles. Moreover, a NOR gate circuit is demonstrated by direct patterning of p-doped channels using laser irradiation without introducing passive layers and metal electrodes with different work functions. This method simplifies device fabrication procedures and shows a promising future in large scale logic circuit applications.     

Scaling the Si MOSFET: from bulk to SOI to bulk

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping     

一维均匀掺杂突变PN结伽马剂量率辐射解析模型

研究硅基半导体集成电路最基本结构之一PN结的伽马剂量率辐射模型,阐明PN剂量率辐射模型的重要意义。根据半导体物理基本方程,推导计算出在剂量率辐射下一维均匀掺杂突变PN结光电流响应的解析解模型,根据解析解,在不同参数下用Mathematica作图观察,并与计算机辅助设计技术(TCAD)数值模拟仿真结果对比,验证解析解的正确性;最后基于解析解,通过分析剂量率、偏压、PN结几何尺寸、掺杂浓度、载流子扩散系数、少子寿命等参数对稳态光电流的影响,提出一个更方便工程计算的稳态光电流模型。     

高速自隔离三重扩散技术研究

本文介绍双极IC中自隔离的三重扩散(3D)技术的特点和工艺路线,给出了采用全离子注入工艺制作的器件特性,探讨了工艺技术中的关键问题,指出,浅结离子注入与退火条件的选择是影响器件性能的主要因素。     

Reverse recovery transient characteristic of PEDOT:PSS/n-Si hybrid organic-inorganic heterojunction

We study the junction behavior of poly (3,4-ethylenedioxythiophene):polystyrenesulphonate/n-Si hybrid organic/inorganic heterojunction by reverse recovery transient (RRT) characterization. RRT response for PEDOT:PSS/n-Si hybrid junction is reported for various n-Si doping concentration and forward bias current injection level. The presence of settling time of 8.3–23.5 μs in the RRT response in contradiction to Schottky junction model commonly assumed for PEDOT:PSS/n-Si hybrid structure. The decrease in the minority carrier lifetime from 126.8 μs to 39.5 μs with increased n-Si doping concentration, suggests that minority carriers are stored at n-Si side of the junction, which is consistent with a p⁺-n junction model for the hybrid structure. The minority carrier lifetime is found to depend on forward bias current injection level, attributed to trap-saturation effect of the recombination-centers at the PEDOT:PSS/n-Si junction. The DC-IV characteristics of the PEDOT:PSS/n-Si hybrid junction are also consistent with the notion of diffusion and trap assisted recombination dominated dark current. The diffusion dominated transport of PEDOT:PSS/n-Si leads to an ideal p⁺-n junction behavior that leverages on the good transport properties of Si. Our findings are important in the modeling and optimization of the characteristics of electronic devices based on the organic/Si hybrid junction.     

浅N~+-P结雪崩电子有效发射的掺杂剖面计算(英文)

A very shallow N-P junction has been produced on a silicon substrate using a low energy ion implantation(≤25keV) followed by suitable annealing. The junction is in parallel to the silicon surface and able to emit electrons out of the surface when biased in avalanche breakdown. The number of emitting electrons significantly depends on doping profiles, junction depth, and work function of the electron emitting material.This paper reports the calculation of the optimum theoretical doping profiles. The calculation indicates that the N+ layer thickness must be of the order of 100A to obtain high efficiency η defined as the number of electrons emission out of Si surface per total number of avalanche electrons. The experimental results of the N+-P junction with desirable doping profiles will also be presented. This topic is the basic investigation for the design and fabrication of vacuum silicon devices.     

碲镉汞多色红外焦平面探测芯片

文章从芯片结构、晶格匹配和PN结性能三个方面对碲镉汞多色焦平面探测芯片技术进行了探讨,结果显示在三种主要的双色探测芯片结构中,单电极和环孔工艺的双色芯片技术相对比较成熟,高难度的刻蚀技术以及所引起的表面反型是制约双电极或多电极多色探测芯片技术发展的主要因素,而环孔技术在发展多色探测芯片方面则有其独到之处,随着探测波段的增加,其工艺难度并没有质的变化。多色探测芯片不同外延层之间的晶格失配以及和Si基衬底之间热失配也是必须加以考虑和解决的一个问题,在现阶段, Si基直接外延、大面积碲锌镉材料和ZnCdTe /Si复合衬底技术并举仍将是明智的选择。在PN结方面,二代焦平面的成结技术在多色器件的宽带结上尚未能够实现,刻蚀反型和深台面侧面钝化的困难依然存在,这些均制约着器件性能的提高,另外,多色芯片的结构和表面加工工艺也影响着探测芯片的光通量利用率和量子效率。