Low-noise operation of buried channel MOS transistors

Results are presented which show that extremely low-noise performance is possible in buried n-channel transistors. By careful choice of operating point, low-noise operation with useful gain is possible. The use of these devices as circuit elements is discussed.     

Noise in buried channel charge-coupled devices

In this paper we discuss the noise measured at the output of a buried channel charge-coupled device (BCCD) linear shift register. The measured noise arises from four sources; the electrical insertion of signal charge, the output amplifier, dark current, and bulk state trapping. In making these measurements the concept of correlated double sampling was used in an output circuit which had a noise level which was equivalent to less than 3O noise electrons. A critical component in this output was a low noise MOSFET which was achieved by use of the buried channel technology. A low noise input structure for electrical insertion of signal charge was used which introduced a signal which had a noise level which ranged from less than 10 e^-to as high as 60 e^-depending on the size of the signal charge. The dark current noise was found to be well characterized as a shot noise and levels on the order of 20 e^-were measured. The above low noise levels made possible direct measurement of the noise due to bulk state trapping, and depending on the signal size and clock rate noise levels were measured which ranged from less than 10 to over 100 noise electrons. One of the most important bulk traps was found to be due to gold impurities which had a density of ∼ 2 × 10¹¹cm^-3.     

MOS field threshold increase by phosphorus-implanted field

The threshold voltage of the field regions of p-channel Si gate devices can be controllably increased by phosphorus ion implantation prior to field oxidation without any additional masking step. For a 1.25-µ field oxide thickness, an increase of more than 20 V in intermediate field threshold can be achieved without lowering junction breakdown voltage.     

Scanning electron microscope measurements on short channel MOS transistors

Several methods are discussed for measurement of PN junction shapes and channel field conditions in short (≈1 μm gate lengths) MOS transistors. A special test structure for short channel MOS transistor measurements with a scanning electron microscope (SEM) is presented. Secondary electron measurements on lased scribed and angle lapped and stained PN junctions are discussed. Methods for sectional imaging of electrically active, cleaved transistors using electron-beam-induced current (EBIC) are presented. An approximate quantitative model of the EBIC imaging process is presented which allows the calculation of current in a MOS transistor. Using this model the current is shown to be dominated by electric field effects in the depletion region of the transistor.     

A gigabit MOS logic circuit with buried channel MOSFETs

An MOS frequency divider operating with gigabit clock rate has been realized to show the potential of MOS logic circuits for high-speed applications. The divider was constructed with buried channel MOSFETs as the basic elements. A master-slave flip-flop that was constructed with the enhancement/depletion type NAND gates was used for the divider. The basic gates were designed using full 1 /spl mu/m patterning rules. For the fabrication of these very fine circuits, photomasks made by an electron-beam system were applied and sputter etching was employed to form fine patterns such as the polysilicon gate and contact holes. The maximum counting frequency of 1.64 GHz and the shortest propagation delay time of 72.5 ps/gate with a fundamental gate were obtained.     

Measurements on depletion-mode field effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices

The properties of bulk transfer charge-coupled devices (BCCD's) may be characterized from measurements obtained using MOS capacitors and field effect transistors. Models are presented for the MOS capacitor and field effect transistor for the case where a shallow doped layer of polarity opposite to that of the substrate is incorporated between the oxide and the substrate. These models explain the observed frequency dependence of the capacitance-voltage (C-V) characteristics of these devices.Techniques are presented for determining the impurity profile of the buried layer from the low frequency C-V measurements made on MOS transistors. The majority carrier mobilities in the buried layer and at the surface are measured for the BCCD's and compared to the surface minority carrier mobility measured for the surface channel CCD's. Generation lifetimes at the surface, in the buried layer and in the underlying substrate are determined from capacitance-time (pulse bias C-t) measurements and leakage current measurements of the MOS capacitors and transistors. Methods are demonstrated whereby the depth from the oxide interface of the potential minimum (depth of the buried channel) and its potential can be determined as a function of the various applied biases.     

Large- and small-signal channel transit time delays in long-channel MOS transistors

Turn-on and turn-off delay times (intrinsic channel transit times) of long-channel MOST's are studied for both large-and small-signal inputs. By developing large-signal dynamic equations in normalized form it is evident that the normalized channel current and voltage distributions are unique and independent of device parameters and applied voltages. Channel transit time delays for both large and small signal are found to be given by a simple analytical expression containing a constant, undefined for large signal but defined explicitly for small signal. Values for the constant are found for large- signal operation in several modes by computer simulation representing the channel as a series of cascaded CCD elements. Those for small signal are found by representing the channel as anRCtransmission line. With the values of the constant determined, the simple analytical expression is shown to accurately predict channel transit time delays regardless of device type, channel length, width, substrate doping, crystal orientation, or effective mobility. It is concluded that the data presented can be used in designing delay lines or low-pass filters employing long-channel devices.     

Understanding wide-band MOS transistors

A quantitative understanding of MOS-transistor speed has been slow to emerge because of the absence of a commonly agreed-upon figure of merit for MOS-transistor speed and a lack of familiarity among designers with MOS-amplifier topologies. It is suggested that these problems can be addressed through the use of the unity-gain current frequency (f _T) as a figure of merit for MOS transistors, the use of f_T in the prediction of amplifier bandwidth, and a wider familiarity among designers with practical examples of MOS wideband amplifiers. The use of f_T as a figure of merit is discussed, and the achievable amplifier bandwidths are determined. Increasing the f_T of an MOS device by making the g_m larger or the C_g smaller, or both, is discussed. Wideband CMOS amplifiers are considered     

A wide range linear variable resistor by buried channel MOS/SIMOX

A low-distortion linear variable resistor using an offset gate buried-channel MOSFET fabricated by SIMOX technology is described. The offset gate structure on the insulating substrate provides 15 to 100 k/spl Omega/ drain-to-source resistance, and 2.5% total harmonic distortion at 100 k/spl Omega/. In a battery-feed circuit application for a subscriber-line interface circuit, the area of a variable conventional polysilicon resistor.     

v-E dependence in small-sized MOS transistors

It is demonstrated that the hyperbolic relation for the v-E dependence which is usually used in transistor modeling, does not hold in short-channel MOSFET's (L_{eff} < 5µm). A new v-E relation is proposed, which is a surface modification of the Scharfetter-Gummel formula and which takes into account the pronounced role of warm electrons. The analysis shows that the lateral electric field at the source determines the transport properties in the channel. A comparison of theoretical results with experimental data is given.     

Conductance of MOS transistors in saturation

The output conductance of MOS transistors operating in the saturation region is studied theoretically and experimentally. A simple physical model is described which accounts for the modification of the electric field in the drain depletion region near the Si-SiO2interface, due to the presence of the gate electrode. The saturation conductance is shown on the basis of this model to be a sensitive function of the oxide thickness as well as the substrate impurity concentration. Good agreement is obtained between theory and experiment over a wide range of device parameters. The characteristics of lowly doped very-short-channel devices, which depart from this theory, are also discussed. The departure is shown to be due to a "punch-through"-type phenomenon.     

Drift velocity saturation in MOS transistors

It is shown that the drift velocity saturation of the current carriers in the channel of a MOSFET iS an important factor in the analysis of the electrical behavior of such devices. The theory presented here, which includes this effect, shows improved agreement with measured output characteristics.     

Modelling of scaled-down MOS transistors

Short-channel MOS transistors exhibit a drain current saturation behaviour different from that of longer channels. By comparing measured and calculated characteristics it is shown that the current increase can be successfully interpreted as a threshold voltage shift proportional to the drain voltage. A circuit model is derived which takes into account the above effect and includes an improved saturation mechanism. Compared with existing models the present one yields smaller deviations between measured and calculated characteristics and does not need non-physical parameters values.     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible     

Noise in integrated-circuit transistors

Recent noise measurement from 1 Hz to 5 kHz on integrated-circuit transistors have shown an anomalous burst noise in addition to the usual noise spectrum. The terminal characteristics of the burst noise are presented and a phenomenological noise-circuit model is developed.     

Low-frequency noise in depletion-mode SIMOX MOS transistors

Low-frequency noise measurements in depletion-mode SIMOX MOSFETs are reported. A simple model provides a reliable interpretation of the low-frequency noise in multi-interface depletion-mode transistors. An experimental procedure to separate noise contributions of front and back interfaces from noise due to bulk carrier fluctuations is described. The noises generated in the thin Si film and at the two Si-SiO₂ interfaces can be identified and characterized independently in terms of bulk properties and interface trap densities. Single-level traps at the back interface and defects in the volume are detected in high-temperature annealed materials     

Electron mobility in n-channel depletion-type MOS transistors

It is found that surface electron mobility can exceed electron mobility in bulk. Field-effect mobilities of n-channel depletion-type MOS transistors were measured, comparing transistorG_{m} - V_{g}and diodeC - V_{g}characteristics. Electron mobility in a highly doped n-type channel layer exceeds that in bulk at around the onset of surface accumulation. This can be explained by reduction in ionized impurity scattering under accumulation conditions. In accumulation conditions, excessive electrons screen the Coulombic field from ionized impurities. This is confirmed by theoretical calculation based on the Maxwell-Boltzmann distribution of electrons and electron-concentration-dependent electron mobility.     

Short-channel MOS transistors in the avalanche-multiplication regime

Short-channel MOS transistors have been analyzed in the avalanche-multiplication regime. Ionization integrals, internal body effect, and parasitic bipolar turn-on have been investigated in dependence of channel doping profile and substrate doping level. Results of a two-dimensional numerical analysis offer a better understanding of the breakdown mechanisms. For devices with shallow channel doping and high-resistivity substrate, an avalanche-current-induced barrier lowering at the source junction edge is observed. Electron injection via this locally lowered barrier triggers parasitic bipolar action. A deep channel implant improves the source barrier and lower substrate resistivity shifts the parasitic bipolar trigger voltage to higher drain voltage (1-1.5 V).