DC self-heating effects modelling in SOI and bulk FinFETs

DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers.     

Two-dimensional analytic modeling of very thin SOI MOSFETs

An analytic solution of the Poisson's equation for MOSFETs on very thin SOI (silicon on insulator) was developed using an infinite series method. The calculation region includes the thin SOI and the gate and buried oxides. The results of this model were found to agree well with a two-dimensional (PISCES) simulation in the subthreshold region and the linear region with small V_DS. This model is used to study the short-channel behavior of very small MOS transistors on thin SOI. It is found that with very thin SOI, short-channel effects are much reduced compared to bulk MOS transistors and depend on the bulk-substrate bias. The model also shows that it is possible to fabricate submicrometer transistors on very thin SOI even if the channel doping is nearly intrinsic     

Short-channel effects in SOI MOSFETs

Short-channel effects in thin-film silicon-on-insulator (SOI) MOSFETs are shown to be unique because of dependences on film thickness and body and back-gate (substrate) biases. These dependences enable control of threshold-voltage reduction, channel-charge enhancement due to a drain bias, carrier velocity saturation, channel-length modulation and its effect on output conductance, as well as device degradation due to hot carriers in short-channel SOI MOSFETs. A short-channel effect exclusive to SOI MOSFETs, back-surface charge modulation, is described. Because of the short-channel effects, the use of SOI MOSFETs in VLSI circuits provides the designer with additional flexibility as compared to bulk-MOSFET design. Various design tradeoffs are discussed     

Simple theory for threshold-voltage modulation in short-channel m.o.s. transistors

The threshold-voltage modulation ?Vr of m.o.s. transistors, due to substrate bias VR, is determined using a simple 2-dimensional approach. It is shown that, for a given substrate bias, the ?VT of short-channel devices is less than that of long-channel devices. It is also shown that the intrinsic (zero substrate bias) threshold voltage of short-channel devices is less than that of long-channel devices. The functional dependence of ?VT on VR is derived, and verified experimentally.     

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.     

Substrate-bias effect and source-drain breakdown characteristics inbody-tied short-channel SOI MOSFET's

The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits     

Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI

MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p⁺-polysilicon gate, and the PMOS devices have an n⁺-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions     

SOI LDMOSFET的背栅特性

在绝缘体上硅衬底上,制备了栅长为0.5μm的低势垒体接触结构和源体紧密接触结构的横向双扩散功率晶体管.详细研究了器件的背栅特性.背栅偏置电压对横向双扩散功率晶体管的前栅亚阈值特性、导通电阻和关态击穿特性均有明显影响.相比于源体紧密接触结构,低势垒体接触结构横向双扩散功率晶体管的背栅效应更小,这是因为低势垒体接触结构更好地抑制了浮体效应和背栅沟道开启.还介绍了一种绝缘体上硅横向双扩散功率晶体管的电路模型,其包含前栅沟道,背栅沟道和背栅偏置决定的串联电阻.     

Characteristics and Fluctuation of Negative Bias Temperature Instability in Si Nanowire Field-Effect Transistors

In this letter, negative bias temperature instability (NBTI) in silicon nanowire field-effect transistors (SNWFETs) is investigated and found to exhibit some new characteristics that are probably due to the structural nature of nanowires. In long-channel SNWFETs, a fast degradation and a quick saturation of NBTI are observed and discussed. In short-channel SNWFETs, a large fluctuation of NBTI is observed, which mainly originates from the ultrasmall gate areas of the short-channel SNWFETs and the statistical nature of randomly trapped charges in the oxide and at the Si/SiO₂ interface. Techniques to suppress the fluctuation and characterize the intrinsic NBTI in ultrasmall SNWFETs are proposed and discussed. A recently developed online gate current method is demonstrated, which effectively alleviates this NBTI fluctuation in SNWFETs.     

Influence of the channel width on the threshold voltage modulation in m.o.s.f.e.t.s

The threshold vollage of an m.o.s. field-effect transistor is modulated by the source-to-substrate reverse bias. In the letter, the theory for long- and short-channel transistors is extended to include the influence of the channel width. The result is an analytical expression for the threshold voltage as a function of geometry and bias that agrees well with experimental data.     

Thermal stress probing the channel-length modulation effect of nano n-type FinFETs

The 3D FinFETs deed provide the impressive gate controllability, especially in drive speed of transistors. However, this advantage relatively brings some drawbacks in channel length modulation (CLM) causing the difficulty in device model establishment. In this work, besides the study of n-type FinFETs in CLM effect, the previous study in 2D HK/MG nMOSFETs at room temperature is also referred and discussed with 3D FinFETs. The influence to the CLM effect at low gate bias is more apparent, speculating the quality of surface channel contributing the depletion width near drain site. The depletion width is usually influenced by raised temperature. And the CLM effect is gradually moved from the low-field dominated to the mid-field as the temperature increased at short-channel device no matter what the V_T implant energy is, but not suitable to the others.     

Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS

Source/drain (S/D) engineering for ideal box-shaped junction formation using laser annealing (LA) combined with pre-amorphization implantation (PAI) is proposed and implemented in device integration for sub-100-nm CMOS on an SOI substrate. Modeling analysis for the resistance component associated with junction profile abruptness demonstrates that a noticeable reduction in parasitic series resistance with technology generation can be achieved through junction profile slope engineering. From the experimental results of LA, it is found that PAI not only controls the ultrashallow junction depth precisely, but also reduces the laser energy fluence required for impurity activation. In addition, laser annealing energy can be further reduced by use of SOI substrates in the device integration, indicating the implementation feasibility of LA to CMOS integration with an enlarged process window margin. The proposed S/D engineering is verified by the sheet resistance of junctions and the fabricated device current characteristics exhibiting substantially improved short-channel performance with higher current capability due to the box-shaped junction profile as compared with conventional rapid thermally-annealed (RTA) devices.     

A study of negative-bias temperature instability of SOI and body-tied FinFETs

Negative-bias temperature-instability (NBTI) characteristics are carefully studied on SOI and body-tied pMOS FinFETs for the first time. It was observed that a narrow fin width degraded device lifetime more than a wider fin width. Electrons generated by the NBT stress are accumulated at the center of a silicon fin and cause energy-band bending. This results in an incremental hole population at the interface. The energy band is bent more steeply at the narrow fin than at the wide fin by the accumulated electrons. A body-tied FinFET shows better immunity to NBT stress due to a substrate contact.     

Improved subthreshold characteristics of n-channel SOI transistors

It has been found that certain n-channel MOSFET's fabricated on silicon-on-insulator (SOI) substrates formed by oxygen implantation can havelog (I_{d}): V_{gs}, characteristics with very steep slopes in the subthreshold region. In contradiction to normal models for short-channel transistors on bulk silicon, the slope becomes steeper for shorter gate lengths or higher drain voltages. This effect is shown to be related to the kink in the output characteristics of transistors with floating islands.     

Numerical study of self-heating effects of MOSFETs fabricated on SOAN substrate

A two-dimensional numerical analysis is performed to investigate the self-heating effects of metal-oxide-silicon field-effect transistors (MOSFETs) fabricated in silicon-on-aluminum nitride (SOAN) substrate. The electrical characteristics and temperature distribution are simulated and compared to those of bulk and standard silicon-on-insulator (SOI) MOSFETs. The SOAN devices are shown to have good leakage and subthreshold characteristics. Furthermore, the channel temperature and negative differential resistance are reduced during high-temperature operation, suggesting that SOAN can mitigate the self-heating penalty effectively. Our study suggests that AlN is a suitable alternative to silicon dioxide as the buried dielectric in SOI, and expands the applications of SOI to high temperature.     

Modes of operation and radiation sensitivity of ultrathin SOItransistors

Improved short-channel behavior, reduced subthreshold slopes, and mobility enhancements previously observed in NMOS transistors made in thin, fully depleted silicon-on-insulator (SOI) films are discussed. These results were obtained with the back interface held in depletion during operation. It is shown from basic principles of device operation that the observed performance improvements are sensitive to the applied substrate voltage. In addition, the exposure of the back interface to the surface depletion region in these devices makes the transistor performance sensitive to radiation-induced charging effects at the back interface. The anticipated effects of radiation on threshold voltage, subthreshold slope, and mobility in ultrathin, fully depleted SOI transistors are discussed, and an estimate is made of the expected radiation sensitivity of these parameters for a typical ultrathin SOI technology     

Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme

The bias scheme of the variable body-factor fully depleted (FD) silicon-on-insulator (SOI) MOSFET, which has been previously proposed, is reexamined. Using a new scheme, the inversion and accumulation on the substrate in the active state can be avoided, and thus, ac performance in the active state is not degraded even with extremely thin buried-oxide (BOX), owing to the depletion of the substrate. Moreover, subthreshold leakage can be sufficiently suppressed in the standby state, owing to extremely thin BOX. This scheme provides threshold-voltage adjustability for the suppression of interdie and within-die variation in the active state. This device scheme is also applicable to multichannel FD SOI MOSFETs including FinFETs with a low-aspect-ratio fin, where the back-bias scheme can be applied     

Output characteristics of short-channel field-effect transistors

A recent model for hot-electron MOS transistors [4], [5] is generalized for short-channel field-effect transistors. It is based on six to seven parameters for the carrier mobility under the influence of transverse and Iongitudinal electric fields, for the threshold voltage and its dependence on drain bias, and for a finite longitudinal field at pinch-off. Such important features of short-channel FET's like reduced available current and voltage gain are well represented, where the latter turns up as important limiting factor in submicron devices. Effects of zero-field mobility, impurities, and device geometry are stated explicitly. The results are confirmed by measured data on 0.9-µm silicon gate MOSFET's.     

Use of zone-melting recrystallization to fabricate a three-dimensional structure incorporating power bipolar and field-effect transistors

Three-dimensional (3-D) structures have been fabricated incorporating power bipolar transistors in a Si substrate and metal-oxide-semiconductor field-effect transistors (MOSFET's) in an overlying silicon-on-insulator (SOI) film that was zone-melting recrystallized with a graphite strip heater. Both N-P-N and P-N-P bipolar transistors were used. The N-P-N devices exhibited no significant change in transistor characteristics after zone-melting recrystallization (ZMR), while the P-N-P devices showed a substantial reduction in breakdown voltage. The MOSFET's exhibited electron mobilities comparable to those in similar devices fabricated in single-crystal Si wafers. The bipolar transistor yield is approximately 90 percent. The unusually high device quality and yield for 3-D structures obtained by the ZMR technique demonstrates the feasibility of fabricating monolithic structures incorporating both logic functions and relatively high-current high-voltage power switches.