Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering

Local voltage dithering provides near optimum savings when workload varies for fine-grained blocks. Combining this approach with sub-threshold operation permits ultra-dynamic voltage scaling from 1.1 V to below 300 mV for a 90-nm test chip. Operating at 330 mV provides minimum energy per cycle at 9/spl times/ less energy than ideal shutdown for reduced performance scenarios. Measurements from the test chip characterize the impact of temperature on the minimum energy point.     

A 1-mm 50 k-Pixel IT CCD image sensor for miniature camera system

The world's smallest image sensor (1-mm 50 k-pixel interline CCD) has been developed. It features an extremely small pixel of 4×4 μm² integration of a V_sub adjust circuit, and a packageless assembly of a chip provided microlens. The resultant chip size and the assembled device outer size are 1.1(H)×1.34(V) mm and 1.2(H)×1.5(V) mm, respectively     

Compact and Efficient Green VECSEL Based on Novel Optical End-Pumping Scheme

We propose a novel lens-less optical end-pumping scheme and report on the development of a highly efficient and compact green vertical-external-cavity surface-emitting laser (VECSEL). A constant-wave pump-power-limited maximum green output power of 1.1 W and an optical-to-optical conversion efficiency of as high as ~15.7% (=1.1 W/7 W) were achieved using a single chip pump laser diode placed directly behind the VECSEL structure without any beam focusing and shaping optical elements.     

基于SN8P2204的RFID高频阅读器设计

提出了一种基于USB接口的非接触式IC卡读卡器的实现方法,重点讨论了符合ISO/IEC 14443A规范的软硬件设计。该读卡器CPU采用了集成USB接口功能的控制芯片SN8P2204,射频芯片使用了Philips公司的兼容ISO/IEC 14443A规范的读卡器专用集成芯片MF RC500,实现了低成本的具有USB接口的非接触式IC读卡器,所设计的IC读卡器完全兼容USB1.1规范。     

CMOS limiting amplifier for SDH STM-16 optical receiver

A 2.5 Gbit/s limiting amplifier is realised in a 0.35 μm CMOS technology. At a supply voltage of 5 V, the power dissipation is 225 mW. The input dynamic range is about 40 dB at a constant output voltage swing (400 mVp-p). The chip area is 1×1.1 mm²     

A subnanosecond clock Josephson 4-bit processor

A Josephson 4-b processor with a 4-bit slice microprocessor, a 4-b multiplier, a 12-b accumulator, an 8-kb ROM, and a sequencer is described. The chip was fabricated with 1.5-μm all-niobium technology, and contains 24000 Nb/AlO_x/Nb Josephson junctions. The processor was designed using a bit slice structure and a simple ripple-carry method, and it has a data sequence based on a three-stage pipeline. Experiments confirmed that the processor functions operated correctly. The critical path measurements for each stage show that the ROM has a 100-ps access time, the microprocessor can be clocked at 1.1 GHz, and the multiplier has a 200-ps multiplication time. The power dissipation of the chip was 6.1 mW     

A Broadband Balanced Distributed Frequency Doubler With a Sharing Collector Line

A broadband balanced distributed frequency doubler fabricated by 0.35 $mu$m SiGe BiCMOS technology is developed to operate from 4 to 18 GHz output frequency. This balanced doubler consists of an active balun and a distributed doubler. A sharing collector line is used in the balanced distributed doubler to reduce the chip size. This circuit exhibits a measured conversion loss of less than 8 dB and a fundamental rejection of better than 23 dB for the output frequency between 4 and 18 GHz. The chip size is 1.1$, times ,$0.7 mm $^{2}$.      

A single-chip 12.7 Mchips/s digital IF BPSK direct sequencespread-spectrum transceiver in 1.2 μm CMOS

This paper describes a fully integrated digital-spread spectrum transceiver chip fabricated through MOSIS in 1.2 μm CMOS. It includes a baseband spread spectrum transmitter and a coherent intermediate frequency (IF) receiver consisting of a Costas loop, an acquisition loop for the pseudo-noise (PN) sequence, and a clock recovery loop with a 406.4 MHz onchip numerically controlled oscillator (NCO). The transceiver is capable of operating at a maximum IF sampling rate of 50.8 MS/s and a maximum chip rate of 12.7 R Mchips/s (Mcps) with selectable data rates of 100, 200, 400, and 800 kbps. At the maximum operating speed of 50.8 R MS/s, it dissipates 1.1 W. In an additive white Gaussian noise channel the IF receiver achieves a receiver output SNR within 1 dB of theory and can acquire code with a wide range of input SNR from -17 dB to over 30 dB. The transceiver chip has been interfaced to an RF up/down converter to demonstrate a wireless voice/data/video link operating in the 902-928 MHz band     

A 1 Mb EEPROM with MONOS memory cell for semiconductor diskapplication

A 1 Mb 5 V-only EEPROM (electrically erasable programmable ROM) with metal-oxide-nitride-oxide-semiconductor (MONOS) memory cells specifically designed for a semiconductor disk application is described. The memory has high endurance to write/erase cycles and a relatively low programming voltage of ±9 V. These advantages result from the structure and the characteristics of the MONOS memory cell. A newly developed dual-gate-type MONOS memory cell has a small unit cell area of 18.4 μm² with 1.2 μm lithography, and the die size of the fabricated chip is 5.3 mm×6.3 mm. A new programming scheme called multiblock erase solved the problem of slow programming speed. A programming speed of up to 1.1 μs/B equivalent (140 ms/chip) was obtained     

A 1.5-V 900-MHz monolithic CMOS fast-switching frequencysynthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-μm CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 × 1.1 mm². The settling time is less than 100 μs and the phase noise is -118 dBc/Hz at 600-kHz offset     

Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator

This paper reports the design and measurement results of a write pulse generator IC for rewritable CD and DVD disk drives implemented in a standard digital 0.35 /spl mu/m CMOS technology. The chip is the interface between a processor and a laser driver. It provides accurate timing signals to the laser driver via a four-level differential current interface. Transitions between current levels are programmable with 149 ps resolution at a data rate of 420 Mb/s, corresponding to 16x DVD write speed. The chip includes a digital core managing the different write strategies, a CMOS serial interface to the processor for programming, a low power, low phase noise, 64-phase ring voltage-controlled oscillator (VCO) based on CMOS inverters, a phase-locked loop (PLL) locking the VCO to the system clock, and a current interface to the laser driver. The PLL phase noise is -144 dBc/Hz at 10 MHz offset from the 105 MHz carrier. At this frequency, the rms jitter is 1.1 ps with 0.8 mA VCO core supply current. The chip is fully ESD protected.     

Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space _* Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a floating point and graphics unit and an advanced cryptographic unit which provides high enough bandwidth to run the two 10 Gb Ethernet ports encrypted at wire speeds. There is a 4 MB Level2 cache on chip. Each of the four on-chip memory controllers controls two FBDIMM channels. Niagara2 has 503 million transistors on a 342 mm² die packaged in a flip-chip glass ceramic package with 1831 pins. The chip is built in Texas Instruments' 65 nm 11LM triple-Vt CMOS process. It operates at 1.4 GHz at 1.1 V and consumes 84 W.     

Performance of multiwavelength simultaneous monitoring circuitemploying arrayed-waveguide grating

This paper proposes a novel multiwavelength simultaneous monitoring (MSM) circuit that uses the wavelength crossover properties of an arrayed-waveguide grating (AWG). The MSM circuit consists of an AWG, a stabilized semiconductor laser as a reference light, and logarithmic amplifiers. The AWG chip is a simple planar-lightwave-circuit chip. It functions as multiple optical filters, and make it possible to monitor multiple wavelengths simultaneously. The MSM circuit, locked to the reference wavelength produced by a semiconductor laser stabilized to the 1547.49 mn ¹³C₂ H₂ absorption line, achieved 10 MHz resolution and 30 MHz stability for 24 h in the stable polarization state. Measurement accuracy of better than 1.1 GHz can be realized even if the state of polarization of the input light fluctuates at random. Multiwavelength simultaneous monitoring is successfully demonstrated using tunable lasers     

Enhancement of the spectral sensitivity of photodiodes for the mid-IR spectral range

A new method is used to raise the spectral sensitivity of photodiodes based on GaSb/GaInAsSb/GaAlAsSb heterostructures for the spectral range 1.1–2.4 μm. It is shown that, with a profile formed as pits on the metal-free unilluminated rear surface area of the photodiode chip, it is possible to improve the spectral sensitivity of the photodiodes at wavelengths in the range 1.8–2.4 μm. The most pronounced increase of up to 53% at the sensitivity maximum, compared with the sensitivity of conventional photodiodes with a fully metallized rear surface of the chip, is observed for photodiodes with shallow pits 30 μm in radius on their rear surface. These devices can find wide application in systems measuring the amount of water in petroleum products and the moisture content of paper, soil and grain.     

A current-mode continuous-time filter for software defined radio solutions

A 3rd-order continuous-time current-mode filter in 65 nm CMOS technology is presented. The filter has a switchable cut-off frequency between 1.1 and 4.4 MHz and is designed for software defined radio on chip (SDR) solutions. An innovative extension to structures in literature is proposed, that allows saving chip area at low cut-off frequencies. Furthermore a mathematical estimation is presented to show the usability of the structure. The realized chip has an active area of 350 μm × 220 μm and consumes 12.3 mW at 1.2 V. The dynamic range for a bandwidth of 1.1 MHz is 77.2 dB, the in-band output current noise is \(31.16\,\hbox{pA}/\sqrt{\hbox{Hz}}\) and the IIP3 is 1.8 mA_p.     

Design Methodology for a 40-GSamples/s Track and Hold Amplifier in 0.18-$muhbox m$SiGe BiCMOS Technology

A 40-GSamples/s track and hold amplifier (THA) is designed and fabricated in 0.18-$muhbox m$SiGe BiCMOS and operates from a 3.6-V supply. The total power consumption is 540 mW with a chip area of 1.1$hbox mm^2$. Time domain measurements demonstrate 40-GHz sampling and$ S$-parameter measurements show a 3-dB bandwidth of 43 GHz in track mode. For 19-GHz input signals, a total harmonic distortion of$-hbox 27~dB$at the 1dB compression point has been measured and a spurious-free dynamic range of 35 dB has been achieved.     

A low substrate leakage junction isolated p-n-p-n crosspoint array

A 4/spl times/8 p-n-p-n crosspoint array for telephone switching networks is described which uses a junction isolated structure to achieve low substrate leakage. The structure uses collector diffusion isolation in conjunction with gold doping to reduce the substrate leakage to less than one part in 10/SUP 5/. This low substrate leakage is shown to be a necessary feature when a solid-state crosspoint is used in a large switching system. The paper includes computer simulated curves of electron and hole density through the doping profile illustrating how the gold doping affects the substrate leakage. The array consists of a 4/spl times/8 matrix of silicon controlled rectifiers each with a gate diode and gate shunting resistor. The layout of the chip, its design constraints and design calculations are described. The chip is fabricated with nitride passivated beam-lead technology and may be packaged in either a hybrid integrated circuit or an 18-lead DIP. The SCR's have forward and reverse leakages of 10 nA at 30 V, a holding current of 1.1 mA, and a gate trigger current of 0.6 mA. With an on-state resistance which typically lies within 9/spl plusmn/1 /spl Omega/ for any matrix path and an off-state capacitance of 1 pF, the chip is suitable for application in the full range of telephone switching systems.     

14W X波段AlGaN/GaN HEMT功率MMIC

报道了研制的SiC衬底AIGaN/GaN HEMT微带结构微波功率MMIC,芯片工艺采用凹槽栅场板结构提高AlGaN/GaNHEMTs的微波功率特性.S参数测试结果表明AlGaN/GaN HEMTs的频率特性随器件的工作电压变化显著.研制的该2级功率MMIC在9～11GHz带内30V工作,输出功率大于10W,功率增益大于12dB,带内峰值输出功率达到14.7W,功率增益为13.7dB,功率附加效率为23%,该芯片尺寸仅为2.0mm×1.1mm.与已发表的X波段AlGaN/GaN HEMT功率MMIC研制结果相比,本项工作在单位毫米栅宽输出功率和芯片单位面积输出功率方面具有优势.     

A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications

This work proposes a communication digital signal processor (DSP) suitable for massive signal processing operations in orthogonal frequency division multiplexing (OFDM) and code-division multiple-access (CDMA) communication systems. The OFDM-based IEEE 802.11a wireless LAN transceiver and CDMA-based WCDMA uplink receiver are simulated to evaluate the computation requirements of future communication systems. The architecture of the communication digital signal processor is established according to the computational complexity of these simulations. The proposed architecture supports basic butterfly operations, single/double-precision and real- and complex-valued multiplication-and-accumulation (MAC), squared error computation, and add-compare-select (ACS) operation. This butterfly/complex MAC architecture can greatly enhance the execution efficiency of operations often found in communication applications. The processor chip is fabricated using a 0.35-/spl mu/m n-well one-poly four-metal CMOS technology. The fabricated DSP chip reaches a speed of 1.1 G MAC/s when operating in the high-speed mode, and it achieves 4 M MAC/s/mW in the low-power mode.     

Monolithic Voltage Controlled Oscillator for X- and Ku-Bands

A GaAs voltage controlled oscillator circuit that tones from 11.15 to 14.39 GHz and 16 to 18.74 GHz has been designed and fabricated. The 1.1 mm x 1.2-mm chip includes two varactors, a 300-µm FET, bypass capacitors, tuning inductors, and isolation resistors. Wide-band circuit design techniques will be described. Varactor and circuit effects causing the noncontinuous bandwidth will be discussed showing the capability of continuous 11 to 18 GHz tuning using a single GaAs chip.