A practical SPICE model based on the physics and characteristics of realistic single-electron transistors

A practical model for a single-electron transistor (SET) was developed based on the physical phenomena in realistic Si SETs, and implemented into a conventional circuit simulator. In the proposed model, the SET current calculated by the analytic model is combined with the parasitic MOSFET characteristics, which have been observed in many recently reported SETs formed on Si nanostructures. The SPICE simulation results were compared with the measured characteristics of the Si SETs. In terms of the bias, temperature, and size dependence of the realistic SET characteristics, an extensive comparison leads to good agreement within a reasonable level of accuracy. This result is noticeable in that a single set of model parameters was used, while considering divergent physical phenomena such as the parasitic MOSFET, the Coulomb oscillation phase shift, and the tunneling resistance modulated by the gate bias. When compared to the measured data, the accuracy of the voltage transfer characteristics of a single-electron inverter obtained from the SPICE simulation was within 15%. This new SPICE model can be applied to estimating the realistic performance of a CMOS/SET hybrid circuit or various SET logic architectures.     

Fabrication and Characterization of Sidewall Defined Silicon-on-Insulator Single-Electron Transistor

We reported the fabrication and characterization of a new type of silicon-on-insulator (SOI) single-electron transistor utilizing usual CMOS sidewall gate structures. We used oxide sidewall spacer layers as well as two poly-Si finger gates on an SOI wire mesa as implantation masks, to form tunnel barriers and thus a quantum dot (QD) that is smaller than the spacing between polygates. Characterization results exhibited clear Coulomb oscillations persisting up to 30 K. The Coulomb energy and the size of the QD extracted from three devices were consistent with the spacing between two poly-Si gates of each device. Furthermore, the junction capacitance of each device was almost constant and only the gate capacitance varied. These analyses suggested that the size of the QD was fully controlled by the process.      

SOI single-electron transistor with low RC delay for logic cells and SET/FET hybrid ICs

We report on a successful fabrication of silicon-based single-electron transistors (SETs) with low RC time constant and their applications to complementary logic cells and SET/field-effect transistor (FET) hybrid integrated circuit. The SETs were fabricated on a silicon-on-insulator (SOI) structure by a pattern-dependent oxidation (PADOX) technique, combined with e-beam lithography. Drain conductances measured at 4.2 K approach large values of the order of microsiemens, exhibiting Coulomb oscillations with peak-to-valley current ratios /spl Gt/1000. Data analysis with a probable mechanism of PADOX yields their intrinsic speeds of /spl sim/ 2 THz, which is within an order of magnitude of the theoretical quantum limit. Incorporating these SETs as basic elements, in-plane side gate-controlled complementary logic cells and SET/FET hybrid integrated circuits were fabricated on an SOI chip. Such an in-plane structure is very efficient in the Si fabrication process, and the side gates adjacent to the electron island could easily control the phase of Coulomb oscillations. The input-output voltage transfer, characteristic of the logic cell, shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2 K. The SET/FET hybrid integrated circuit consisting of one SET and three FETs yields a high-voltage gain and power amplification with a wide-range output window for driving the next circuit. The small SET input gate voltage of 30 mV is finally converted to 400 mV, corresponding to an amplification ratio of 13.     

Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

As a solution to the high speed, ultralow power, and extremely compact ADC circuit block, a complementary single-electron transistor (SET)/CMOS hybrid amplifier-based analog-to-digital converter (ADC) is proposed. It is implemented with a physics-based SPICE model including nonideal effects in real Si-based SET_s such as the tunnel barrier lowering effect, parasitic MOSFET_s operation, and the phase shift of Coulomb oscillation by the bias of a gate other than a main control gate. Its core scheme is the combination of both the amplification of SET current by MOSFET_s and the suppression of a Coulomb blockade oscillation valley current by the differential amplification. In addition, the transient operation of SET/CMOS hybrid circuit-based ADC_s fully accounting for nonideal effects of real SET_s is successfully demonstrated for the first time. Compared with the previous SET-based ADC_s, our ADC makes features of the immunity to nonideal effects, large voltage swing of the output signal, and high load drivability.     

A dual-gate-controlled single-electron transistor using self-aligned polysilicon sidewall spacer gates on silicon-on-insulator nanowire

A dual-gate-controlled single-electron transistor was fabricated by using self-aligned polysilicon sidewall spacer gates on a silicon-on-insulator nanowire. The quantum dot formed by the electric field effect of the dual-gate structure was miniaturized to smaller than the state-of-the-art feature size, through a combination of electron beam lithography, oxidation, and polysilicon sidewall spacer gate formation processes. The device shows typical MOSFET I-V characteristics at room temperature. However, the Coulomb gap and Coulomb oscillations are clearly observed at 4 K.     

Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors

Single-electron transistors that have electrical tunneling barriers are fabricated, and Coulomb oscillation peaks and negative differential transconductance are observed at room temperature (300 K). Operation characteristics and multioscillation peaks are further investigated at low temperature (80 K). The period of Coulomb oscillation is 2.3 V due to an ultrasmall control gate capacitance, and oscillation peaks are shifted through the side gate bias, which is explained by the derived stability plot for dual-gate structures. Even with the side gates electrically floating, the device still operates as a single-electron transistor since the p-n junction barrier plays a role of tunneling barrier. In addition, by changing the bias condition, double dots are formed along the channel and peak splitting is observed.     

Temperature Dependence of Coulomb Oscillations on DNA-Mediated Au Nanoparticle Assembly

We fabricated a single-electron transistor using DNA-assisted assembly of Au nanoparticles. Most devices exhibited clear Coulomb blockade and oscillations. In contrast to conventional single-electron transistors, however, the period of Coulomb oscillations was observed to depend on the temperature. This temperature dependence is probably ascribed to the temperature dependence of gate capacitance.     

Fabrication of single-electron transistors using field-emission-induced electromigration

We report a novel technique for the fabrication of planar-type Ni-based single-electron transistors (SETs) using electromigration method induced by field emission current. The method is so-called "activation" and is demonstrated using arrow-shaped Ni nanogap electrodes with initial gap separations of 21-68 nm. Using the activation method, we are easily able to obtain the SETs by Fowler-Nordheim (F-N) field emission current passing through the nanogap electrodes. The F-N field emission current plays an important role in triggering the migration of Ni atoms. The nanogap is narrowed because of the transfer of Ni atoms from source to drain electrode. In the activation procedure, we defined the magnitude of a preset current Is and monitored the current I between the nanogap electrodes by applying voltage V. When the current I reached a preset current Is, we stopped the voltage V. As a result, the tunnel resistance of the nanogaps was decreased from the order of 100 T(omega) to 100 k(omega) with increasing the preset current Is from 1 nA to 150 microA. Especially, the devices formed by the activation with the preset current from 100 nA to 1.5 microA exhibited Coulomb blockade phenomena at room temperature. Coulomb blockade voltage of the devices was clearly modulated by the gate voltage quasi-periodically, resulting in the formation of multiple tunnel junctions of the SETs at room temperature. By increasing the preset current from 100 nA to 1.5 microA in the activation scheme, the charging energy of the SETs at room temperature was decreased, ranging from 1030 meV to 320 meV. Therefore, it is found that the charging energy and the number of islands of the SETs are controllable by the preset current during the activation. These results clearly imply that the activation procedure allows us to easily and simply fabricate planar-type Ni-based SETs operating at room temperature.     

Single electron transistor with P-type sidewall spacer gates

A single-electron transistor (SET) is one of the promising solutions to overcome the scaling limit of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Up to now, various kinds of SETs are being proposed and SETs with a dual gate (DG) structure using an electrical potential barrier have been demonstrated for room temperature operation. To operate DG-SETs, however, extra bias of side gates is necessary. It causes new problems that the electrode for side gates and the extra bias for electrical barrier increase the complexity in circuit design and operation power consumption, respectively. For the reason, a new mechanism using work function (WF) difference is applied to operate a SET at room temperature by three electrodes. Its structure consists of an undoped active region, a control gate, n-doped source/drain electrodes, and metal/silicide or p-type silicon side gates, and a SET with metal/silicide gates or p-type silicon gates forms tunnel barriers induced by work function between an undoped channel and grounded side gates. Via simulation, the effectiveness of the new mechanism is confirmed through various silicide materials that have different WF values. Furthermore, by considering the realistic conditions of the fabrication process, SET with p-type sidewall spacer gates was designed, and its brief fabrication process was introduced. The characteristics of its electrical barrier and the controllability of its control gate were also confirmed via simulation. Finally, a single-hole transistor with n-type sidewall spacer gates was designed.     

Realization of multiple valued logic and memory by hybrid SETMOS architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.     

Few electron limit of n-type metal oxide semiconductor single electron transistors

We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.     

Observation of negative differential resistance and single-electron tunneling in electromigrated break junctions

We observed a negative differential resistance (NDR) along with single-electron tunneling (SET) in the electron transport of electromigrated break junctions with metal-free tetraphenylporphyrin (H₂BSTBPP) at a temperature of 11 K. The NDR strongly depended on the applied gate voltages, and appeared only in the electron tunneling region of the Coulomb diamond. We could explain the mechanism of this new type of electron transport by a model assuming a molecular Coulomb island and local density of states of the source and the drain electrodes.     

Effects of oxidation process on the tunneling barrier structures in room-temperature operating silicon single-electron transistors

We investigate the tunneling barrier structures in the room-temperature operating silicon single-electron transistors (SETs). The devices are fabricated in the form of the point-contact channel metal-oxide-semiconductor field-effect transistors with gate oxide formed by thermal oxidation or low-pressure chemical vapor deposition (LP-CVD). From the gate voltage and temperature dependence of the peak current in the SET characteristics, it is found that the thermal oxidation process leads to higher and narrower tunneling barriers. In some SETs with CVD-deposited gate oxide, thermally activated conduction over the low tunneling barriers is clearly observed in a wide temperature range from 100 K-300 K.     

Integration of single-electron transistors using field-emission-induced electromigration

A novel technique for the integration of planar-type single-electron transistors (SETs) composed of nanogaps is presented. This technique is based on the electromigration procedure, which is caused by a field emission current. The technique is called "activation." By applying the activation to the nanogaps, SETs can be easily obtained. Furthermore, the charging energy of the SETs can be controlled by adjusting the magnitude of the applied current during the activation process. The integration of two SETs was achieved by passing a field emission current through two series-connected initial nanogaps. The current-voltage (I(D)-V(D)) curves of the simultaneously activated devices exhibited clear electrical-current suppression at a low-bias voltage at 16 K, which is known as the Coulomb blockade. The Coulomb blockade voltage of each device was also obviously modulated by the gate voltage. In addition, the two SETs, which were integrated by the activation procedure, exhibited similar electrical properties, and their charging energy decreased uniformly with increasing the preset current during the activation. These results indicate that the activation procedure allows the simple and easy integration of planar-type SETs.     

Josephson Junction based Quantum Computing

Among the physical realizations of the elements required for quantum computation nano-scale electronic devices [2, 10, 12, 16] are very promising. They can be easily integrated into electronic circuits and scaled up to large numbers of qubits. Here we describe qubits based on low-capacitance Josephson junctions. In these systems Coulomb blockade effects allow the control of the charge on a superconducting island. They constitute quantum bits, with logical states differing by the charge on one island. Single- and two-bit operations can be performed by manipulating applied gate voltages. The phase coherence time is sufficiently long to allow a series of these steps. In addition to the manipulation of qubits, the resulting quantum state can be read out by coupling a single-electron transistor capacitively to the qubit. Received: October 23, 1998; revised version: September 21, 1999     

Fluctuation of average position of electrons in Coulomb island in Si single-electron transistor

Average position of electrons along thickness direction in a Coulomb island in an n-channel Si single-electron transistor is estimated by analyzing the back-gate voltage dependence of peak voltage (defined as the gate voltage giving a drain current peak) as a function of peak number. It is found that the accuracy of estimated average position is better than 0.5 nm and that the average position fluctuates as the peak number increases.     

Large Coulomb blockade oscillations at room temperature in ultranarrow wire channel MOSFETs formed by slight oxidation process

We propose a new fabrication technique of room-temperature operating silicon single-electron transistors (SETs). The devices are in the form of ultranarrow wire channel MOSFETs, where a sub-10-nm channel is formed by wet etching and slight thermal oxidation. Large Coulomb blockade (CB) oscillations whose peak-to-valley current ratio at room temperature is as high as 6.8 are observed in the fabricated ultranarrow wire channel MOSFETs. It is found that larger CB oscillations are obtained in the ultranarrow wire channel SETs than in the point-contact channel SETs. It is considered that the potential fluctuations induced during the channel formation processes give rise to multiple-dot SET structures in the ultranarrow wire channel MOSFETs.     

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

In this article we review the fundamental properties and applications of sidewall GaAs tunnel junctions. Heavily impurity-doped GaAs epitaxial layers were prepared using molecular layer epitaxy (MLE), in which intermittent injections of precursors in ultrahigh vacuum were applied, and sidewall tunnel junctions were fabricated using a combination of device mesa wet etching of the GaAs MLE layer and low-temperature area-selective regrowth. The fabricated tunnel junctions on the GaAs sidewall with normal mesa orientation showed a record peak current density of 35 000 A cm^-2. They can potentially be used as terahertz devices such as a tunnel injection transit time effect diode or an ideal static induction transistor.     

Sidewall GaAs tunnel junctions fabricated using molecular layer epitaxy

Abstract

In this article we review the fundamental properties and applications of sidewall GaAs tunnel junctions. Heavily impurity-doped GaAs epitaxial layers were prepared using molecular layer epitaxy (MLE), in which intermittent injections of precursors in ultrahigh vacuum were applied, and sidewall tunnel junctions were fabricated using a combination of device mesa wet etching of the GaAs MLE layer and low-temperature area-selective regrowth. The fabricated tunnel junctions on the GaAs sidewall with normal mesa orientation showed a record peak current density of 35 000 A cm^-2. They can potentially be used as terahertz devices such as a tunnel injection transit time effect diode or an ideal static induction transistor.     

Binary adders of multigate single-electron transistors: specific design using pass-transistor logic

We describe how to construct area-efficient adders using single-electron transistors (SETs). The design is based on pass-transistor logic and multigate SETs are used as pass transistors. The proposed design enables us to construct a full adder using only six SETs. We also show that multibit binary adders can be built using cascaded SET structures without any long wires. The small number of transistors and no-metal-interconnection configuration significantly reduces the circuit area and capacitance to be charged. A Monte Carlo simulation shows that even when the inter-SET-node capacitances are reduced and consequently the carry signal level terribly fluctuates in its path due to single-electron charging effects, the carry can correctly propagate as long as the final output node capacitance is sufficiently large. This proves that the area reduction and speed improvement are compatible in our design. We also discuss the possibility of large-scale integration, touching on the random-offset-charge issue.