铁电负电容场效应晶体管器件的研究

铁电负电容场效应晶体管作为一种新型半导体器件,利用铁电材料的负电容效应可使晶体管的亚阈值摆幅突破理论极限值60 mV/dec,是未来低功耗晶体管领域最具有前途的器件之一。该文研究并建立了铁电负电容场效应晶体管的器件模型,采用Matlab软件对负电容场效应晶体管的器件特性进行了研究分析,获得了亚阈值摆幅为33.917 6 mV/dec的负电容场效应晶体管的器件结构,探究了铁电层厚度、等效栅氧化层厚度及不同铁电材料对负电容场效应晶体管亚阈值摆幅的影响。     

NC-FinFET器件的仿真研究

通过结合BSIMCMG模型与负电容(NC)模型,构建了NC-FinFET模型。基于所建立的NC-FinFET模型,推导分析了其等效电容模型。利用Hspice对NC-FinFET的器件特性进行了系统仿真与分析。结果表明,与FinFET相比,NC-FinFET在电学特性上有更加明显的优势,亚阈值摆幅更低。此外,分析了铁电材料的厚度对亚阈值摆幅及栅压放大倍数的影响,以及衬偏电压对NC-FinFET性能的影响,为在NC-FinFET中降低功耗和抑制寄生效应提供了理论依据和解决思路。     

SOI铁电负电容晶体管亚阈值特性研究

随着微电子技术进入纳米领域,功耗成为制约技术发展的主要因素,因此,低功耗器件成为半导体器件领域的研究热点。负电容场效应晶体管基于铁电材料的负电容效应可有效地降低器件的亚阈值摆幅,从而降低器件的功耗。该文设计了一种基于绝缘体上硅(SOI)结构的铁电负电容场效应晶体管,利用TCAD Sentaurus仿真工具对负电容晶体管进行仿真研究,得到了亚阈值摆幅为30.931 mV/dec的负电容场效应晶体管的器件结构和参数。最后仿真研究了铁电层厚度、等效栅氧化层厚度对负电容场效应晶体管亚阈值特性的影响。     

质子辐照对AlGaN/GaN HEMT亚阈值摆幅特性的影响

研究了具有不同栅漏间距的AlGaN/GaN高电子迁移率晶体管(HEMT)的亚阈值摆幅特性在0.4 MeV质子辐照(质子总注量为2.16×10¹² cm^-2)后的变化规律。质子辐照前，各器件的亚阈值摆幅基本一致；质子辐照后，器件的亚阈值摆幅随着栅漏间距的减小而逐渐降低。基于辐照前后器件的电容-电压曲线和输出特性得到低场载流子输运特性，并据此分析了亚阈值摆幅的变化原因。发现与器件尺寸相关的极化散射效应是不同尺寸器件在辐照后亚阈值摆幅发生不同变化的主要原因。为AlGaN/GaN HEMT的性能优化提供了全新的视角与维度。     

短沟道双栅MOSFET的亚阈值特性分析

基于泊松方程和拉普拉斯方程,结合双栅MOSFET的边界条件,采用牛顿-拉夫逊迭代法推导了双栅MOSFET亚阈值区全沟道的电势解析解。在亚阈值区电流密度方程的基础上,提出了双栅MOSFET的一个亚阈值电流模型,并获得了亚阈值摆幅的解析公式。通过对物理模型和数值模拟结果进行比较,发现在不同的器件结构参数下,亚阈值摆幅之间的误差均小于5%。     

短沟道三材料柱状围栅MOSFET的解析模型

在柱坐标系下利用电势的抛物线近似,求解二维泊松方程得到了短沟道三材料柱状围栅金属氧化物半导体场效应管的中心及表面电势。推导了器件阈值电压、亚阈值区电流和亚阈值摆幅的解析模型,分析了沟道直径、栅氧化层厚度和三栅长度比对阈值电压、亚阈值区电流和亚阈值摆幅的影响。利用Atlas对具有不同结构参数的器件进行了模拟研究和比较分析。结果表明,基于解析模型得到的计算值与模拟值一致,验证了所建模型的准确性,为设计和应用此类新型器件提供了理论基础。     

栅宽对AlGaN/GaN HEMTs亚阈值摆幅的影响

制备了不同栅极宽度的AlGaN/GaN高电子迁移率晶体管，通过测量各器件电容-电压曲线和转移特性曲线，得到了栅沟道载流子输运特性以及亚阈值摆幅，结果显示当栅极宽度从10μm增加到50μm时，亚阈值摆幅下降了40.3%.定性且定量地分析了亚阈值摆幅值随栅极宽度变化的原因，发现不同的栅极宽度对应不同的极化散射强度，亚阈值摆幅的变化是由栅沟道载流子输运特性和极化散射效应造成的.为AlGaN/GaN高电子迁移率晶体管开关性能优化提供了新的视角与维度，将促进其更好地应用于无线通信、电力传输以及国防军工领域.     

AlGaN/GaN HEMT凹栅槽结构器件的频率特性

采用一系列不同栅长和结构的T型栅器件来研究凹栅槽结构抑制短沟道效应和提高频率特性的作用.随着栅长不断缩短,短沟道效应逐渐明显,栅长从300 nm缩短至100 nm时,亚阈值摆幅逐渐增大,栅对沟道载流子的控制变弱,且器件出现软夹断现象.凹栅槽结构可以降低器件的亚阈值接幅,提高开关比,栅长100 nm常规结构器件的亚阈值摆幅为140 mV/dec,开关比为106,而凹栅槽结构器件的亚阈值摆幅下降为95 mV/dec,开关比增大为107,凹栅槽结构明显抑制了短沟道效应.在漏源电压为20 V时,100 nm栅长的凹栅槽结构器件的截止频率和最高振荡频率达到了65.9和191 GHz,同常规结构相比,分别提高了5.78％和4.49％.由于凹栅槽结构缩短了栅金属到二维电子气(2DEG)沟道的间距,增大了纵横比,所以能够改善器件的频率特性.     

短沟道无结柱状围栅MOSFET的解析模型

通过在柱坐标系下求解二维泊松方程,建立了短沟道无结柱状围栅金属氧化物半导体场效应管的电势模型,并推导了阈值电压、亚阈值区电流和亚阈值摆幅的解析模型。在此基础上,分析了沟道长度、沟道直径和栅氧化层厚度等参数对阈值电压、亚阈值区电流和亚阈值摆幅的影响。最后,利用Atlas软件对器件进行了模拟研究。结果表明,根据解析模型得到的计算值与模拟值一致,验证了模型的准确性。这些模型可为设计和应用新型的短沟道无结柱状围栅金属氧化物半导体场效应管提供理论基础。     

具有86 mV/dec亚阈值摆幅的MoS_2/SiO_2场效应晶体管（英文）

在SiO_2/Si(P~(++))衬底上制备了多层MoS_2背栅器件并进行了测试.通过合理优化和采用10 nm SiO_2栅氧,得到了良好的亚阈值摆幅86 mV/dec和约107倍的电流开关比.该器件具有较小的亚阈值摆幅和较小的回滞幅度,表明该器件具有较少的界面态/氧化物基团吸附物.由栅极漏电造成的漏极电流噪声淹没了该器件在小电流(~10~(-13)A)处的信号,限制了其开关比测量范围.基于本文以及前人工作中MoS_2器件的表现,基于薄层SiO_2栅氧的MoS_2器件表现出了良好的性能和潜力,显示出丰富的应用前景.     

A new process-variation-immunity method for extracting capacitancecoupling coefficients in flash memory cells

Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I_D=I₀ exp[q(V_GB - nV_SB)/nkT], a mathematical formulation of the subthreshold swing ratio in the subthreshold slope method is constructed to isolate the measurement errors caused by process variations from the errors traditionally caused by bulk capacitance coupling. To minimize the effect of process variations, a new method is developed based on the model. In this method, the control gate voltage shift due to weak body effect is measured in flash memory cells in subthreshold, while the corresponding slope factor n is adequately deduced from threshold voltage versus source-to-substrate bias measurement in dummy devices. The corrected capacitance coupling coefficients show large improvements compared to the design values, and the updated errors are found to be close to that caused solely by bulk capacitance coupling. The method is also fast since only a small source-to-substrate bias of 0.1 V is needed for implementation of weak body effect, and thereby it can be used as an in-line monitor of capacitance coupling coefficients     

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing

This paper presents the concept of a new field effect transistor based on ferroelectric insulator. The proposed design is named Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material and silicon-on-insulator (SOI) device. The structure varies from the conventional SOI technology by substituting the buried SiO₂ with a layer of ferroelectric insulator. This new material stack can extract an effective negative capacitance (NC) in the body of the device. The NC effect can provide internal signal boosting. It is demonstrated that the subthreshold swing and the threshold voltage of the proposed device can be lowered by carefully selecting the doping density, the types of the gate oxide and the thicknesses of the ferroelectric film, the silicon layer above the buried insulator and the gate oxide. Lower subthreshold swing is a prime requirement for ultra-low-power design. This paper focuses on studying several parameters to tune the subthreshold swing of the SOFFET device. We have recently introduced the concept of the new transistor, SOFFET, with ferroelectric insulator embedded inside the silicon substrate to lower the subthreshold swing. This paper investigates the impacts of different oxide materials, ferroelectric thicknesses and doping profiles on the negative capacitance inside the body of the proposed PD-SOFFET. It is observed that some emerging gate oxide materials can improve subthreshold flexibility, lower leakage and provide better control over the channel in the proposed device.     

Analysis of subthreshold carrier transport for ultimate DGMOSFET

A novel transport model for the subthreshold mode of double-gate MOSFETs (DGMOSFETs) is proposed in this paper. The model enables the analysis of short-channel effects (SCEs) such as the subthreshold swing (SS), the threshold-voltage rolloff, and the drain-induced barrier lowering. The proposed model includes the effects of thermionic emission and the quantum tunneling of carriers through the source-drain barrier. An approximative solution of the two-dimensional Poisson equation is used for the distribution of the electric potential, and the Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The model is verified by comparing the SS with numerical simulations. The new model is used to investigate the subthreshold characteristics of a DGMOSFET having the gate length in the nanometer range with an ultrathin gate oxide and channel thickness. The SCEs degrade the subthreshold characteristics of DGMOSFETs when the gate length is reduced below 10 nm, and any design in the sub-10-nm-regime should include the effects of quantum tunneling.     

Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon-germanium substrates

The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLAS^TM by Silvaco Inc.     

Modeling the subthreshold swing in MOSFET's

This letter reports on the bias-dependence of the inverse subthreshold slope or subthreshold swing in MOSFET's. It is shown by calculations and verified by experiments that the subthreshold swing varies with gate bias and exhibits a global minimum. The gate-source voltage for which minimum subthreshold swing is reached, is linearly related to the voltage at which moderate inversion starts. Influence of oxide thickness and temperature is investigated. The subthreshold swing is an important parameter in modeling the weak inversion regime, especially for high-gain analog applications, imaging circuits, and low-voltage applications. Based on calculations of the subthreshold swing, we propose a new model for the diffusion component of the drain leakage current in MOSFET's. The model accurately predicts the temperature dependence of the drain leakage current     

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.     

Two-dimensional simulation and measurement of high-performanceMOSFETs made on a very thin SOI film

Thinning effects on the device characteristics of silicon-on-insulator (SOI) MOSFETs are discussed. Two-dimensional/two-carrier device simulation revealed the following advantages. An n-channel MOSFET with 500-Å-SOI thickness exhibited a high-punchthrough resistance as well as an improved subthreshold swing down to a deep submicrometer region, even if the film was nearly intrinsic. A capacitance coupling model has been proposed to explain these subthreshold characteristics. The kink elimination effect, which was attributed to a significantly reduced hole density in the SOI film, was reproduced. The low-field channel mobility exhibited a significant increase, which was ascribed to a decrease in the vertical electric field. Moreover, the current-overshoot phenomenon associated with the switching operation was suppressed. Excess holes recombine with electrons quickly after the gate turn-on, bringing about a stabilized potential in the SOI substrate. Experiments were also carried out to verify the simulation     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.     

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs

An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is presented. Two-dimensional Poisson equation is solved analytically using series method and channel potential is obtained. The analytical expression for subthreshold swing is achieved. Model results are compared with Medici simulation results, both of them turn out to agree very well. The results show the variation of channel potential and subthreshold swing with channel length, gate bias, and oxide thickness, which will provide some guidance for the integrated circuit designs.