共查询到17条相似文献,搜索用时 93 毫秒
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针对传统全差分运算放大器电路存在输入输出摆幅小和共模抑制比低的问题,提出了一种高共模抑制比轨到轨全差分运算放大器电路。电路的输入级采用基于电流补偿技术的互补差分输入对,实现较大的输入信号摆幅;中间级采用折叠式共源共栅结构,获得较大的增益和输出摆幅;输出级采用共模反馈环路控制的A类输出结构,同时对共模反馈环路进行密勒补偿,提高电路的共模抑制比和环路稳定性。提出的全差分运算放大器电路基于中芯国际(SMIC) 0.13μm CMOS工艺设计,结果表明,该电路在3.3 V供电电压下,负载电容为5 pF时,可实现轨到轨的输入输出信号摆幅;当输入共模电平为1.65 V时,直流增益为108.9 dB,相位裕度为77.5°,单位增益带宽为12.71 MHz;共模反馈环路增益为97.7 dB,相位裕度为71.3°;共模抑制比为237.7 dB,电源抑制比为209.6 dB,等效输入参考噪声为37.9 nV/Hz1/2@100 kHz。 相似文献
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介绍了一种应用于超低EMI无滤波D类音频功放的全差分运算放大器结构,可构成积分器,起滤除高次谐波的作用。该运算放大器采用两级结构来获得高增益,第一级为折叠共源共栅,偏置电路采用反馈结构,给整个运算放大器提供偏置电流,从而提高电路的电源抑制比;采用伪AB类输出级提高运放的瞬态响应,稳定运放输出。仿真结果表明,该电路具有良好的性能:增益为113dB,相位裕度为67°;单位增益带宽为1.9MHz,共模抑制比为160dB,电源抑制比为82.7dB;共模反馈环路增益为120dB,相位裕度为62°。 相似文献
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针对传统运算放大器共模抑制比和电源抑制比低的问题,设计了一种差分输入结构的折叠式共源共栅放大器。本设计采用两级结构,第一级为差分结构的折叠式共源共栅放大器,并采用MOS管作为电阻,进一步提高增益、共模抑制比和电源电压抑制比;第二级采用以NMOS为负载的共源放大器结构,提高增益和输出摆幅。基于LITE—ON40V1.0μm工艺,采用Spectre对电路进行仿真。仿真结果表明,电路交流增益为125.8dB,相位裕度为62.8°,共模抑制比140.9dB,电源电压抑制比125.5dB。 相似文献
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低噪声高共模抑制比的运算放大器是将套筒式共源共栅结构、差分输出和共模负反馈相结合,设计出的一种新型运算放大器.基于SMIC0.18 μm工艺模型对电路进行设计,仿真结果表明该电路的开环增益为82.3 dB,相位裕度为66°,共模抑制比为122 dB,增益平坦带宽为15 MHz,噪声为7.781 nV/sqrt (Hz),达到设计要求. 相似文献
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设计实现了一种具有高增益大带宽的全差分增益自举运算放大器,适用于高速高精度流水线模数转换器采保电路的应用.增益自举放大器的主放大器和子放大器均采用折叠共源共栅式全差分结构,并且主放大器采用开关电容共模反馈来稳定输出电压.该放大器工作在3.0 V电源电压下,单端负载为2pF,采用0.18Wn CMOS工艺库对电路进行仿真,结果显示该放大器的直流增益可达到112dB,单位增益带宽为1.17GHz. 相似文献
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A high-swing CMOS telescopic operational amplifier 总被引:1,自引:0,他引:1
A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulated-cascode differential gain enhancement and a replica-tail feedback technique. A prototype of the op-amp has been built in a 0.81-μm CMOS process. Operating from a power supply of 3.3 V, it achieves a differential swing of ±2.15 V, a differential gain of 90 dB, unity-gain frequency of 90 MHz, and >50-dB CMRR. It is shown, analytically and through simulations, that the operational amplifier maintains its high CMRR even at high frequencies 相似文献
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《Solid-State Circuits, IEEE Journal of》1980,15(2):214-221
The common-mode rejection ratio (CMRR) of differential amplifier stages is treated by means of the matrix analysis of networks with the amplifier gain elements represented as four-pole devices. Two generalized CMRR equations are obtained in terms of imbalances in the transconductance and open-circuit voltage gain parameters of the composiste devices for both the resistor-loaded stage and the current-mirror-loaded stage, respectively. The nonlinear characteristic of the current mirror load has also been derived, and it is demonstrated that the high load sensitivity of CMRR in stages loaded by current mirrors is due to the mirror's nonlinearity. The effects of the second stage of an operational amplifier on its CMRR are considered. The CMRR expressions for a number of typical stages incorporating source resistances are given, and the experimental results with these stages are discussed in detail. 相似文献
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设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线(Pipelined)ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。 相似文献
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Ivanov V. Zhou J. Filanovsky I. M. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(5):397-401
A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current source with a stable drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail. This is obtained by controlling the bulk bias of the input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors. The gain is improved by using gain boost in the current mirrors, and by the suppression of impact ionization current in the output stage 相似文献
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A three op-amps instrumentation amplifier (I.A) with active dc suppression is presented. dc suppression is achieved by means of a controlled floating source at the input stage, to compensate electrode and op-amps offset voltages. This isolated floating source is built around an optical-isolated device using a general-purpose optocoupler, working as a photovoltaic generator. The proposed circuit has many interesting characteristics regarding simplicity and cost, while preserving common mode rejection ratio (CMRR) and high input impedance characteristics of the classic three op-amps I.A. As an example, a biopotential amplifier with a gain of 80 dB, a lower cutoff frequency of 0.1 Hz, and a dc input range of +/- 8 mV was built and tested. Using general-purpose op-amps, a CMRR of 105 was achieved without trimmings. 相似文献
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基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极(Common Base, CB)电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。 相似文献