A novel offset gated polysilicon thin film transistor without anadditional offset mask

We have proposed a novel offset gated polysilicon TFT fabricated without an offset mask in order to reduce leakage current and suppress the kink effect. The photolithographic process steps of the new TFT device are identical to those of conventional non-offset structure TFT's and an additional mask to fabricate an offset structure is not required in our device. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The novel TFT also exhibits a considerable reduction in the kink effect because a very thin film TFT may be easily fabricated due to the elimination of the contact over-etch problem     

Narrow width effects of bottom-gate polysilicon thin filmtransistors

The effects of channel width on the characteristics of both hydrogenated and unhydrogenated bottom-gate polysilicon thin-film transistors (TFTs) were investigated in detailed. For unhydrogenated and silane gas formed TFTs, a drastic decrease in threshold voltage is observed due to the grain-boundary traps are reduced when the channel width is reduced to less than grain size, but the minimum drain current sensitive to intragranular tail states are nearly unchanged. After hydrogenation, almost grain boundary traps and intragranular tail states were passivated, the effect of traps along poly channel edges caused by the definition of poly channel pattern will dominate, i.e., threshold voltage and minimum drain current increase with decreasing channel width. Also disilane gas formed TFTs are studied for comparison     

A self-aligned offset polysilicon thin-film transistor usingphotoresist reflow

A simple fabrication method for a self-aligned offset structure, which uses photoresist reflow, is developed to reduce the leakage current of polysilicon thin-film transistors (poly-Si TFTs). The reflow of photoresist can be controlled by varying photoresist thickness and reflow temperature. It is found that the reflow length increases in proportion to the photoresist thickness, and increases with increasing reflow temperature at less than 200°C for the AZ5214A photoresist. Poly-Si TFTs are successfully demonstrated with offset lengths of 0.4 and 0.6 μm, which show apparent reduction of the leakage current     

A novel PMOS SOI polysilicon transistor

An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude     

A vertical submicron polysilicon thin-film transistor using a lowtemperature process

This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (⩽600°C). The channel length is determined by the thickness of an SiO₂ film. As a result, submicron vertical polysilicon TFT's can be fabricated without submicron lithographic equipment that is not yet available for large area active matrix liquid crystal display (AMLCD) applications. The device has a dynamic range of greater than five orders of magnitude after hydrogenation     

A low-leakage-current CdSe thin film transistor

This paper reports the design, fabrication, and performance of a very low-leakage-current thin film transistor (TFT). The TFT had a double-gate structure and used a 80–100 Å thick CdSe thin film as the semiconductor. The free charge carrier concentration in the semiconductor film was calculated to be 5×10¹⁴/cm³. These factors contributed to achieving a zero-gate-bias current less than 10^?10 A in the TFT. The ON/OFF current ratio of the TFT was measured to be greater than 10⁶. The TFT had acceptable stability in the ON condition and excellent stability in the OFF condition. A life test was performed on a TFT under a zero-gate-bias condition. After 1100 hr of testing, the zero-gate-bias current of the TFT increased from 5.8×10^?10 A to 9×10^?10 A. With extrapolation, the TFT had more than 10,000 hr lifetime.     

Threshold voltage adjustment of organic thin film transistor by introducing a polysilicon floating gate

The structure of organic thin film transistors (OTFTs) is optimized by introducing a floating gate into the gate dielectric to reduce the threshold voltage of OTFTs. Then the optimized device is simulated, and the simulation results show that the threshold voltage of optimized device is reduced by about 10 V. The reduction of the threshold voltage is helpful and useful for the application of OTFTs in many areas. In addition, this way of reducing the threshold voltage of OTFT is compatible with traditional silicon technology and can be used in manufacturing.     

引入悬浮栅对有机薄膜晶体管的阈值电压进行调整

The structure of organic thin film transistors (OTFTs) is optimized by introducing floating gate into the gate dielectric to reduce the threshold voltage of OTFTs in this article. Then the optimized device is simulated and the results of the simulation show the threshold voltage of optimized device is reduced by about 10 V. The reduction of the threshold voltage is helpful and useful for the application of OTFTs in many areas. In addition, this way to reduce threshold voltage of OTFT is compatible with traditional silicon technology and can be used in manufacture.     

A novel polysilicon thin-film transistor with a p-n-p structuredgate electrode

We propose and fabricate a novel polycrystalline silicon thin-film transistor (poly-Si TFT) which exhibits the properties of an offset gated structure in the OFF state, while acting as a nonoffset structure in the ON state. The fabrication process is compatible with the conventional nonoffset poly-Si TFT's process and does not require any additional mask. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device. It is observed that the ON/OFF current ratio of the proposed poly-Si TFT is improved remarkably     

A true polysilicon emitter transistor

A polysilicon emitter transistor has been fabricated in which the metallurgical base/emitter junction coincides with the interface between polycrystalline and monocrystalline material. The emitter region was formed by deposition of heavily phosphorus-doped polysilicon in an LPCVD reactor at 627°C, a temperature low enough to prevent diffusion of phosphorus into the substrate. Emitter Gummel numbers of over 10¹⁴scm^-4have been obtained with this structure, allowing common emitter current gains in excess of 10000 to be reached for base implant doses of 10¹²cm^-2.     

A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (⩽600°C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity     

Field-effect transistor with diphthalocyanine thin film

A field effect transistor has been fabricated with organic semiconductors: scandium diphthalocyanine and nickel phthalocyanine. The electrical characteristics are studied in air atmosphere. The influence of the diphthalocyanine film thickness has been detected     

Implementation of fully self-aligned bottom-gate MOS transistor

This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.     

Enhanced channel mobility in polysilicon thin film transistors

Due to scattering by charged grain boundaries, carrier mobility μ in the channel of polysilicon thin film transistors (TFT) is usually much lower than the bulk silicon value. We have studied a series of _p-channel TFT devices with varying gate oxide thicknesses d_ox and found that CL shows a strong increase when d_ox is reduced below 150 Å. We attribute this effect to the screening of the charged grain boundary by the gate conductor. The screening becomes effective when the characteristic length associated with the potential barrier at charged grain boundaries becomes comparable to the optical distance between the grain boundary charge and its mirror image in the gate electrode. From the known structure parameters the onset of the strong screening is estimated to occur at oxide thicknesses of about 100 Å     

A new self-aligned offset staggered polysilicon thin-filmtransistor

A new self-aligned offset staggered polysilicon thin-film transistor (poly-Si TFT) has been proposed and demonstrated to have a suppressed leakage current. For the self-aligned offset structure, planarization with thick photoresist and etchback of photoresist are successfully utilized. The offset length can be easily controlled by the thickness of the gate material without photolithographic limitation. In the self-aligned offset polysilicon TFT's, the leakage current decreases with an increasing offset length     

High-voltage silicon thin film transistor on quartz

A high voltage enhancement-type thin film transistor (TFT) has been fabricated on quartz in layers of laser-recrystallized polysilicon. The fabrication details and TFT characteristics are described.     

Stability of polysilicon thin film transistors under switch operating

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique. The drain and source regions are in-situ doped during the LPCVD deposition by using phosphine to fabricate n-type transistors. The active layer and the drain arid source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm²/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec.As these TFTs are commonly used as switching devices in the most of applications in large area electronics field, the study of their stability under AC electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress and then the degradation of polysilicon TFTs is over-estimated when it is checked from the effects of DC gate bias stress.Degradation under bias stress is shown to originate from the creation of gap states at the channel-interface oxide and in the channel material. The lower influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress.     

A physical model of floating body effects in polysilicon thin film transistors

Based on a closed form of the base–emitter voltage of the parasitic bipolar transistor, a physical model of floating body effects is proposed for polysilicon thin film transistors, which takes into account the polysilicon graded pn junction and the generation rate including the Poole-Frenkel effect. Simulated results by this model are in good agreement with experimental data. It is shown that the action of a parasitic bipolar transistor should be taken into account only when the channel length is short enough due to the much smaller carrier mobility in polysilicon compared with single crystalline silicon. Whereas, the parasitic bipolar transistor gain (β) increases sharply with decreasing the channel length when the channel length is less than 5 μm, which is due to the rapid increase of the base transport factor (_T).