High-mobility poly-Si TFTs fabricated on flexible stainless-steelsubstrates

High mobility polycrystalline Si thin-film transistors (poly-Si TFTs) are firstly fabricated on flexible stainless-steel substrates 100 μm thick through low-temperature processes where both active Si and gate SiO₂ films are deposited by glow-discharge sputtering and the Si films are crystallized by KrF excimer laser irradiation. The gate SiO₂ films are sputter-deposited in oxygen atmosphere from the SiO₂ target. Resulting poly-Si TFTs show excellent characteristics of mobility of 106 cm²/V·s and drain current on-off ratio of as high as 1×10⁶. Thus, the poly-Si TFTs are very promising for realizing novel flat panel displays of lightweight and rugged LCDs and LEDs     

High-mobility pentacene thin-film transistors with copolymer-gate dielectric

Pentacene thin-film transistors have been obtained using polymethyl-methacrylate-co-glyciclyl-methacrylate (PMMA-GMA) as the gate dielectric. The optimum active layer thickness in thin-film transistors (OTFTs) was investigated. The present devices show a wide operation voltage range. The on/off current ratio is as high as 10⁵. In linear region (), the field-effect mobility of device increases with the increase in gate field at low-voltage region (), and a mobility of 0.33 cm²/V s can be obtained when . In saturation region, the mobility increases linearly with the gate field, and a high mobility of 1.14 cm²/V s can be obtained at . The influence of voltage on mobility of device was investigated.     

Polycrystalline silicon thin-film transistors fabricated by rapid Joule heating method

We report n- and p-channel polycrystalline silicon thin film transistors (poly-Si TFTs) fabricated with a rapid joule heating method. Crystallization of 50-nm-thick silicon films and activation of phosphorus and boron atoms were successfully achieved by rapid heat diffusion via 300-nm-thick SiO/sub 2/ intermediate layers from joule heating induced by electrical current flowing in chromium strips. The effective carrier mobility and the threshold voltage were 570 cm/sup 2//Vs and 1.8 V for n-channel TFTs, and 270 cm/sup 2//Vs and -2.8 V for p-channel TFTs, respectively.     

Extraction of trap densities in entire bandgap of poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on process conditions of post annealing

Trap densities (D_t) in entire bandgaps of poly-Si thin-film transistors (TFTs) fabricated by solid-phase crystallization (SPC) have been extracted by measuring low-frequency capacitance-voltage characteristics and using an extraction algorithm. The extraction algorithm is explained in detail. D_t in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs, respectively. It is found that D_t is very roughly 10¹⁸ cm⁻³ eV⁻¹ near the midgap and becomes tail states near the conduction and valence bands. As a result, D_t is distributed like U shape in the bandgap, but humps appear around the midgap. Moreover, the dependence of D_t on process conditions of post annealing has been evaluated. It is found that the hump can be reduced by increasing annealing temperature and time because crystal defects generated during the SPC are extinguished during the post annealing.     

High-mobility CMOS transistors fabricated on very thin SOS films

It is reported that the mobility of CMOS transistors fabricated on very thin silicon-on-sapphire (SOS) films is a function of the film growth rate. Transistors with mobilities nearly as high as those obtained on 1.0-μm-thick films have been fabricated on SOS films 0.2 μm thick that have been grown at growth rates above 4 μm/min     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

The metal-induced crystallization of poly-Si and the mobility enhancement of thin film transistors fabricated on a glass substrate

In this study, we report on the fabrication of poly-crystalline silicon (poly-Si) using the metal-induced crystallization (MIC) method and its application to thin film transistors (TFTs). The top gate of the p-type TFTs, whose active layer used MIC poly-Si annealed for 1 h at 650 °C, showed a field effect mobility (μ_FE) of 7.5 cm²/V s. By increasing the crystallization time to 5 h, the quality of the MIC poly-Si was improved. The μ_FE increased from 7.5 to 15 cm²/V s. In order to enhance the channel mobility, the Si dangling bonds, which were produced during the transformation from the amorphous phase to the poly-crystalline phase of silicon (Si), were reduced by using plasma hydrogenation. Measurements show that the μ_FE reached 45 cm²/V s after passivation by an inductively coupled plasma chemical vapor deposition (ICPCVD) system.     

Polycrystalline silicon thin-film transistors fabricated by defect reduction methods

Fabrication of n-channel polycrystalline silicon thin-film transistors (poly-Si TFTs) at a low temperature is reported. 13.56 MHz-oxygen plasma at a 100 W, 130 Pa at 250/spl deg/C for 5 min, and heat treatment at 260/spl deg/C with 1.3/spl times/10/sup 6/-Pa-H/sub 2/O vapor for 3 h were applied to reduction of the density of defect states in 25-nm-thick silicon films crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Defect reduction was numerically analyzed. Those treatments resulted in a high carrier mobility of 830 cm/sup 2//Vs and a low threshold voltage of 1.5 V at a laser crystallization energy density of 285 mJ/cm/sup 2/.     

Low temperature poly-Si thin-film transistor fabrication bymetal-induced lateral crystallization

A new low temperature crystallization method for poly-Si TFTs was developed: Metal-Induced Lateral Crystallization (MILC). The a-Si film in the channel area of a TFT was laterally crystallized from the source/drain area, on which an ultrathin nickel layer was deposited before annealing. The a-channel poly-Si TFTs fabricated at 500°C by MILC showed a mobility of 121 cm²/V·s, a threshold voltage of 1.2 V, and an on/off current ratio of higher than 10⁶ . These electrical properties are much better than TFTs fabricated by conventional crystallization at 600°C     

An integrated photodetector-amplifier using a-Si p-i-n photodiodesand poly-Si thin-film transistors

The authors propose a photodetector-amplifier circuit consisting of a bridge photodetector circuit and a CMOS differential amplifier, both monolithically integrated on a transparent substrate. A test circuit was fabricated using a-Si p-i-n photodiodes and poly-Si thin-film transistors on a quartz substrate. A clear effect of the differential amplifier was demonstrated in the test circuit. It is shown that the circuit performance can be controlled by changing the bias current of the differential amplifier. With a relatively low bias current on the order of 10^-11 A, the circuit works digitally with output voltages either close to 0 V or V_DD. The power consumption of the circuit is approximately 60 μW, which is low enough for use in two-dimensional arrays     

Thin-film transistors fabricated with poly-Si films crystallized atlow temperature by microwave annealing

Solid phase crystallization of amorphous silicon films for poly-Si thin film transistors (TFTs) has advantages of low cost and excellent uniformity, but the crystallization temperature is too high. Using a microwave annealing method, we lowered the crystallization temperature and shortened the crystallization time. The complete crystallization time at 550°C was within 2 h. The device parameters of TFTs with the poly-Si films crystallized by microwave annealing were similar to those of TFTs with the poly-Si films crystallized by conventional furnace annealing. The new crystallization method seems attractive because of low crystallization temperature, short crystallization time, and comparable film properties     

Electric field-enhanced metal-induced lateral crystallization and P-channel poly-Si TFTs fabricated by it

The poly-Si thin film was obtained by electric field-enhanced metal-induced lateral crystallization technique at low temperature. Raman spectra, X-ray diffraction (XRD) and scan electron microscope (SEM) were used to analyze the crystallization state, crystal structure and surface morphology of the poly-Si thin film. Results show that the poly-Si has good crystallinity, and the electric field has the effect of enhancing the crystallization when DC electric voltage is added to the film during annealing. Secondary ion mass spectroscopy (SIMS) shows that the metal Ni improves the crystallization by diffusing into the a-Si thin film, so the crystallization of the lateral diffused region of Ni is the best. The p-channel poly-Si thin film transistors (TFTs) were fabricated by this large-size grain technique. The I_DS−V_DS and the transfer characteristics of the TFTs were measured, from which, the hole mobility of TFTs was 65 cm²/V s, the on and off current ratio was 5×10⁶. It is a promising method to fabricate high-performance poly-Si TFTs at low temperature for applications in AMLCD and AMOLED.     

High-mobility organic thin-film transistors based on a small-molecule semiconductor deposited in vacuum and by solution shearing

The small-molecule organic semiconductor 2,9-di-decyl-dinaphtho-[2,3-b:2′,3′-f]-thieno-[3,2-b]-thiophene (C₁₀-DNTT) was used to fabricate bottom-gate, top-contact thin-film transistors (TFTs) in which the semiconductor layer was prepared either by vacuum deposition or by solution shearing. The maximum effective charge-carrier mobility of TFTs with vacuum-deposited C₁₀-DNTT is 8.5 cm²/V s for a nominal semiconductor thickness of 10 nm and a substrate temperature during the semiconductor deposition of 80 °C. Scanning electron microscopy analysis reveals the growth of small, isolated islands that begin to coalesce into a flat conducting layer when the nominal thickness exceeds 4 nm. The morphology of the vacuum-deposited semiconductor layers is dominated by tall lamellae that are formed during the deposition, except at very high substrate temperatures. Atomic force microscopy and X-ray diffraction measurements indicate that the C₁₀-DNTT molecules stand approximately upright with respect to the substrate surface, both in the flat conducting layer near the surface and within the lamellae. Using the transmission line method on TFTs with channel lengths ranging from 10 to 100 μm, a relatively small contact resistance of 0.33 kΩ cm was determined. TFTs with the C₁₀-DNTT layer prepared by solution shearing exhibit a pronounced anisotropy of the electrical performance: TFTs with the channel oriented parallel to the shearing direction have an average carrier mobility of (2.8 ± 0.3) cm²/V s, while TFTs with the channel oriented perpendicular to the shearing direction have a somewhat smaller average mobility of (1.3 ± 0.1) cm²/V s.     

Low-temperature polysilicon thin-film transistors fabricated fromlaser-processed sputtered-silicon films

In an effort to develop a simple low-temperature high-performance polysilicon thin-film transistor (TFT) technology, we report a fabrication process featuring laser-crystallized sputtered-silicon films. This top Al-gate coplanar TFT process subjects the substrate to a maximum temperature of 300°C, and produces devices with mobilities up to 450 cm²/Vs, on/off current ratios greater than 10⁷ , without using a post-hydrogenation step. We believe these results represent the highest performance TFT's to date fabricated from sputtered silicon films     

The effects of electrical stress and temperature on the propertiesof polycrystalline silicon thin-film transistors fabricated by metalinduced lateral crystallization

An asymmetric Ni-offset method was proposed to improve the electrical properties of poly-Si thin-film transistors (TFTs) fabricated by metal-induced lateral crystallization (MILC). The MILC/MILC boundary, which was inevitably located within the channel when formed by symmetric Ni-offset, could be successfully extracted from channel region by new asymmetric Ni-offset method. Therefore, thus fabricated TFTs showed lower leakage current and better thermal stability than symmetric Ni-offset TFTs. In addition, the effects of electrical stress and temperature on the electrical properties of symmetric/asymmetric Ni-offset TFTs were investigated     

A novel four-mask-processed poly-Si TFT fabricated using excimer laser crystallization of an edge-thickened a-Si active island

A four-mask-processed polycrystalline silicon thin-film transistor (poly-Si TFT) is fabricated using 50-pulse KrF excimer laser to crystallize an edge-thickened amorphous silicon (a-Si) active island without any shrinkage. This method introduces a temperature gradient in the island to enlarge grains from the edge, especially when the channel width is narrow. The grain boundaries across the width of the channel suppress the leakage current and the drain-induced barrier lowering. Moreover, the proposed poly-Si TFT with a channel length of L = 2 /spl mu/m and a channel width of W = 1.2 /spl mu/m possesses a high field-effect mobility of 260 cm/sup 2//Vs and an on/off current ratio of 2.31 /spl times/ 10/sup 8/.     

A poly-Si TFT fabricated by excimer laser recrystallization onfloating active structure

This letter reports a. new excimer laser annealing (ELA) method to produce large polycrystalline silicon (poly-Si) lateral grains exceeding 4 μm. A selectively floating amorphous silicon (a-Si) flint with a 50 nm-thick air-gap was irradiated by a single-pulse XeCl excimer laser and uniform lateral grains were grown due to the lateral thermal gradient caused by the low thermal conductivity of the air. A poly-Si thin-film transistor (TFT) with two high-quality 4.6 μm-long lateral grains was fabricated by employing the proposed ELA and high field-effect mobility of 331 cm²/Vsec was obtained due to. the high-quality grain structure     

Characteristics of top-gate thin-film transistors fabricated onnitrogen-implanted polysilicon films

The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2×10¹²-2×10¹⁴ ions/cm² were investigated in this work. The experimental results showed that nitrogen implanted into polysilicon followed by an 850°C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H₂-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved. Moreover, the hot-carrier reliability was also improved. A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's     

Spatially resolving the hot carrier degradations of poly-Si thin-film transistors using a novel test structure

A novel thin-film transistor test structure is proposed for monitoring the device hot-carrier (HC) degradations. The new test structure consists of several source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. This unique feature allows, for the first time, the study of spatial resolution of HC degradations along the channel of the test transistor after stressing. The extent of degradation as well as the major degradation mechanisms along the channel of the test transistor can be clearly identified.     

High-performance poly-Si TFTs made by Ni-mediated crystallization through low-shot laser annealing

High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been fabricated using metal-induced crystallization followed by laser annealing (L-MIC). Laser annealing after MIC was found to yield a major improvement to the electrical characteristics of poly-Si TFTs. At a laser fluence of 330 mJ/cm/sup 2/, the field effect mobility increased from 71 to 239 cm/sup 2//Vs, and the minimum leakage current reduced from around 3.0/spl times/10/sup -12/ A//spl mu/m to 2.9/spl times/10/sup -13/ A//spl mu/m at a drain voltage of 5 V. In addition, the dependence of the TFT characteristics on the laser energy density was much weaker than that for conventional excimer laser annealed poly-Si TFTs.