线路速率缓存的重端口交换机方案及行为分析

伴随着世界经济的快速发展,我国国内的经济形势也在日新月异的发生着变化,而网络的出现和更新更是无时无刻不在影响着我们的生活,同时,人们对网络存在的要求也逐渐变得更高.在因特网中的交换机,也就是所说的路由器现如今面临着两种挑战,一种是高交换速率的挑战,一种是联网服务质量（QOS）的挑战.高交换速率的挑战需要交换机/路由器尽可能的通过链路速率进行工作,联网服务质量（QOS）需要要求交换机/路由器可以完全仿效输出队列（OQ/outputqueuing）交换机的方式行为.到目前为止,联合输入输出队列（CIOQ/combined input-output queuing）的设计方案与交换机/路由器的不同,它需要交换机/路由器的内部速率加速到原有的2倍.为了满足这种技术的要求,重端口交换机（DPS/duplicated ports switch）的并行技术设计方案应运而生.这套方案有效证明了仿照交换机输出队列（OQ）的行为,以2为端口重数的必要充分性,并且这套方案的使用交换机/路由器可以工作在输入链路速率上,它的行为同交换机/路由器（OQ）的行为是等价的.     

贝加莱（B＆R）-全集成手持式面板

详情点击http://www.vertinfo.com资料索号0323EISX(M)系列提供传统性能如自动协商,10/100 Mbps速率,半双工/全双工工作方式及流量控制,它的先进功能包括:☆ VLAN 端口允许配置物理网络成多个虚拟局域网;☆ 中继(Trunking),允许端口组合为四个,充当与另一EISC相连的高速中继;☆ 服务质量(QoS) , 为交换机接收信息提供优先权。支持的方案有三种:基于端口优先权、基于MAC地址优先权、基于802.1p优先权;☆ 可编程出错继电器提供给监控系统一干接点,一旦交换机侦测到一异常情况,包括链路断开或链路增加;☆ 与网卡或另一集线器相连仅需使…     

全光分组交换路由器缓存需求研究

针对当前只能在一个集成光电芯片上实现容量为几十个分组的光先来先服务（FCFS）缓存,大规模的光缓存仍无法实现的问题,利用接入链路速率远小于骨干链路速率这一特性,在牺牲25％的链路利用率的条件下,讨论小缓存能否满足采用CIOQ缓存队列的全光分组交换路由器的性能需求。从理论上证明采用CIOQ缓存队列的路由器的缓存需求小于采用OQ缓存队列的缓存需求,通过分析和仿真发现,20个分组的缓存即可满性能需求。     

完全自主知识产权 曙光龙芯防火墙

8月14日,Linksys发布了千兆位高级智能交换机SLM224G2。它提供24个10/ 100Mbps以太网端口,且带有2个10/100/ 1000Mbps自适应的铜缆接口或可选光缆(SFP)接口,为接入用户提供从网络边缘到网络核心的千兆上行链路。     

SpaceFibre总线路由器的设计

为实现SpaceFibre标准协议中网络层的功能,提出一种以FPGA为核心的路由器设计方案.根据协议的规范,设计出5个端口的路由器,包括4个普通端口和1个配置端口,每个普通端口有4条虚拟通道.考虑到虚拟通道路由依然存在数据阻塞的可能,在交叉开关矩阵(CrossBar)结构上增添轮询仲裁的路由算法.用Verilog代码实...     

CiSCO满仓千兆位

Cisco系统公司近日宣布进一步增强Catalyst 5000系列,并发布了一系列适用于Catalyst5000系列和Cisco 7500高端路由器系列的千兆位联网解决方案。所推出的新产品包括Catalyst5505、Supervisor Ⅲ交换机、NetFlow特性卡(NFFC)、千兆位以太网上行链路、OC-12模块、三端口千兆位以太网交换模块、9端口干兆位EtherChannel(交换模块,适用于Cisco 7500路由器系列)、千兆位以太网接口处理器(GEIPs)。 Catalyst 5000系列的千兆位以     

3ComSwitch4300交换机测试手记

3Com公司2001年推出SuperStack 3系列的Switch 4300交换机是拥有48个端口的10/100Mbps独立型智能交换机,背板带宽28Gb,定位于高密度、高性能、低成本的第二层交换,并可扩冲多达4条具有链路汇聚(Link Aggregation)功能的千兆上连链路(1000BASE-T和     

VPN扩展企业虚拟网

锐捷网络在充分了解了兴业公司的实际需求后,提出如下建议方案。局域网的实现在网络建议方案中,公司总部及各分公司根据实际测算的数据流量和终端数量,以及各业务系统要求的结构层次,分别选用锐捷网络STAR-S4909骨干路由交换机(最多可以提供16个线速的个千兆端口或64个10/100MRJ45端口)和STAR-S2126G/50G千兆智能交换机(最多可以提供24/48个10/100MRJ45端口和2个千兆扩展插槽),通过百兆和千兆链路连接,实现主干千兆、百兆交换到桌面的网络,满足客户对数据、语音、视频信息在局域网内传送的要求。ExtranetVPN的实现在总部到各分公司…     

Cabletron智能网络优化甘肃169网

甘肃省169网的主干底层连接为SDH环，在SDH环上连接帧中继交换机形成全省的帧中继主干，连接带宽原仅为2M。而原有的各地中心路由器亦以2M的帧中继链路连接到帧中继主干节点交换机上。很明显，这样的主干链路带宽太低，已远远不能满足现有的通信要求。并且，原主干结构采用的IPoverFrame RelavoverSDH的数据传输模式，     

NBase-Xylex公司的工作组级交换机 四种模块随你选

NBase-Xyplex公司在中国推出高性能OptiSwitch800交换机,适用于企业网络中的工作组级。OptiSwitch800可容纳8个高速模块,提供了高达16Gbps的第二层交换带宽。OptiSwitch800交换系统具有8个插槽,可以任意组合安装下列模块:单/双口千兆以太网模块(MM、SM),8口10/100自动协商模块,2/4/8口100Base-FX模块(MM、SM),4/8口MT-RJ 100Base-FX模块。专为工作组以及中型企业网络开发的OptiSwitch800交换机可支持多达14个千兆位端口及64个100Base-FX端口或64个10/100Mbps的自适应端口。对IEEE 802.1q VLAN标记技术、多达12K的大型MAC地址表、智能地址识别机制以及集成流量控制与背压(Backpressure)(IEEE 802.3x)保证了它甚至在网络使用高峰期都可以提供最大功效。端口干线技术通过将多达8个端口组合为一个逻辑链路提供了在交换机与服务器之间增加吞吐量的廉价途径。OptiSwitch800强大的VLAN引擎对全     

在CICQ交换结构下实现分布式的输入排队DRR分组公平调度

传统的基于crossbar的输入排队交换结构在提供良好的QoS方面存在很大的不足,而CICQ(combined input and crosspoint buffered queuing)交换结构与传统的交换结构比,不但能在各种输入流下提供接近输出排队的吞吐率,而且能提供良好的QoS支持。基于CICQ结构,提出了在输入排队条件下实现基于流的分布式DRR分组公平调度算法的方案,并通过仿真验证了这一方案的有效性。     

CICQ交换的流控实现机制和交叉点缓存容量分析

传统的基于crossbar的输入排队交换结构在提供良好的QOS方面存在很大的不足，而CICQ（combined input and crosspoint buffered queuing）交换结构与传统的交换结构相比，不但能在各种输入流下提供接近输出排队的吞吐率，而且能提供良好的QoS支持。文章分析了CICQ结构的流控实现机制，讨论了基于信用的流控机制的开销和实现方案，对crosspoint缓存容鼍作了分析，给出了在各种存储器写入条件下，保持交换结构100％吞吐率所需的最小缓存容量。     

低加速比下输出端排队交换结构的性能分析

摘要：在已有的研究中,为了使输出端排队（oQ）交换结构满足理想的吞吐率和传输时延性能,需要其内部加速比等于交换端口数．将从理论上推导加速比小于交换端口数的情况下OQ交换结构的信元丢包率和传输时延．并利用数值计算的方法证明：只要达到一定的加速比（小于满加速比）,OQ结构就能达到满加速比时的性能。     

A performance model of partial packet discard and early packet discard schemes in ATM switches

In this paper, we develop a concise performance model of partial packet discard (PPD) and early packet discard (EPD) schemes in ATM switches. We study the performance of PPD and EPD with heterogeneous traffic sources. The sources included Poisson, and ON–OFF with long-tailed sojourn time distribution, which is approximated by a hyperexponential distribution. The fairness of EPD is investigated. We automatically generate and numerically solve the underlying Markov chain using a high-level graphical paradigm known as the stochastic reward net. Our numerical results reveal that: (1) the benefit of PPD and EPD is not significant when the queuing system is underloaded with Poisson sources; (2) PPD and EPD can increase the goodput when the system is overloaded or loaded with ON–OFF sources; (3) in All Poisson case, PPD and EPD provide nearly fair service to the sources; (4) the ON–OFF source gets higher goodput than the Poisson source. Because the burstiness of a source will be alleviated by the statistical multiplexing of ATM switches, the ON–OFF source may be viewed as the source that just enters the network, and the Poisson source may be viewed as the source being far away from the network node we are considering and has been regulated and smoothed by the switches it traversed. Therefore, the queuing system with EPD algorithm gives a higher goodput to the sources near it. And the sources far away from the system will have lower goodput. One of our principal conclusions is that per-VC-based scheme is not needed at the core of large ATM networks because the traffic is less bursty at the core of the networks and PPD and EPD are fair under this kind of environment. A per-VC-based scheme may be used at the edge of the ATM cloud. Such a configuration can make the core of the ATM network work at high speed.     

Multicast support in multi-chip centralized schedulers in Input Queued switches

IQ switches store packets at input ports to avoid the memory speedup required by OQ switches. However, packet schedulers are needed to determine an I/O (input/output) interconnection pattern that avoids conflicts among packets at output ports. Today, centralized, single-chip, scheduler implementation are largely dominant. In the near future, the multi-chip scheduler implementation will be needed to reduce the hardware scheduler complexity in very large, high-speed, switches. However, the multi-chip implementation implies introducing a non-negligible delay among input and output selectors used to determine the I/O interconnection pattern at each time slot. This delay, mainly due to inter-chip latency, requires modifications to traditional scheduling algorithms, which normally rely on the hypothesis that information exchange among selectors can be performed with negligible delay. We propose a novel multicast scheduler, named IMRR, an extension of a previously proposed multicast scheduling algorithm named mRRM, making it suitable to a multi-chip implementation, and examine its performance by simulation.     

支持多优先级分组交换调度算法研究及其调度器设计

输入缓存交换结构的特点是缓存器和交换结构的运行速率与端口速率相等、实现容易,但存在队头阻塞。如果采用虚拟输出排队方法和适当的分组调度算法可予以消除,使吞吐率达到100%。文章首先研究讨论了并行迭代匹配算法,滑动迭代匹配调度算法的基本原理、迭代仲裁步骤及其硬件实现;对高速分组交换调度算法的性能进行了分析比较。然后给出了在高速输入队列交换机中实现多优先级调度算法的调度器设计与实现方案。经设计实现证明高速分组交换调度算法不仅硬件实现简单,而且具有良好的特性。     

A proportional feedback scheme for ATM networks

Available bit rate (ABR) service class is proposed by Asynchronous Transfer Mode (ATM) Forum to provide the “best-effort” services like traditional TCP/IP traffic. It is designed to make use of the remaining bandwidth not used by VBR and CBR. However, the bursty nature of ABR traffic makes it difficult to prevent buffers on ATM switches from overflowing. A number of schemes have been proposed for ABR traffic control. In this paper, a proportional scheme that is rate-based hop-by-hop flow control is proposed. A mathematical model is built to analyze the hop-by-hop flow control scheme. It is shown the scheme can utilize full bandwidth without any cell loss. It is also shown the scheme has low queuing delay and fast transient response.     

Invariance of the stationary distribution of states of networks with multimode service, different types of requests, and discriminatory processor sharing

Open and closed queuing networks with multimode strategies and several types of requests are studied. Single-line nodes can operate in several modes. The time spent in each mode has an exponential distribution. The queuing discipline of the server is the discriminatory processor sharing (DPS). The number of requests is a random variable with an arbitrary distribution function. The invariance is established of the stationary distribution of the probabilities of the network states with respect to the functional form of the distributions of the work required to service the requests.     

Controlling mean queuing delay under multi-class bursty and correlated traffic

This paper presents an adaptive queue management scheme to maintain queuing delay in a router at a required level based on a comprehensive analytical model under aggregated Internet traffic flows from various traffic classes. The proposed scheme uses a closed-loop feedback control mechanism to constrain the average queuing delay by regulating traffic arrival rate implicitly through a movable queuing threshold. A discrete-time queuing model is developed to derive the relationship between average queuing delays and queuing thresholds based on a traffic model that models aggregated Internet traffic through superposition of N MMBP-2 arrival processes. The queuing threshold is adjusted dynamically with reference to the relationship derived in the analytical model and also feedback of average queuing delay measurement. Packets are dropped dynamically with respect to the changes of queuing threshold and the packet loss events serve as implicit congestion indicators. Matlab is used to perform queuing analysis and simulation. Statistical evaluation is performed to show the efficiency and accuracy of the analytical and simulation results.