6H-SiC MOS场效应晶体管的研制

报道了多晶硅栅 6 H- Si C MOS场效应器件的制造工艺和器件性能。 6 H- Si C氧化层的SIMS分析说明在氧化过程中 ,多余的 C以 CO的形式释放 ,铝元素逸出极少 ,氧化层中因有较多的铝而正电荷密度较大 ,Si C的氧化速率和掺杂类型关系不大。器件漏电流都有很好的饱和特性 ,最大跨导为 0 .36 m S/ mm ,沟道电子迁移率约为 14cm2 / V.s,但串联电阻效应明显。     

1800 V NPN bipolar junction transistors in 4H-SiC

The first high voltage npn bipolar junction transistors (BJTs) in 4H-SiC have been demonstrated. The BJTs were able to block 1800 V in common emitter mode and showed a peak current gain of 20 and an on-resistance of 10.8 mΩ·cm² at room temperature (I_C=2.7 A @ V_CE=2 V for a 1 mm×1.4 mm active area), which outperforms all SiC power switching devices reported to date. Temperature-stable current gain was observed for these devices. This is due to the higher percent ionization of the deep level acceptor atoms in the base region at elevated temperatures, which offsets the effects of increased minority carrier lifetime at high temperatures. These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

各向异性6H-SiC MOSFET击穿的温度特性

分析了不同晶面上温度对 6H-Si C MOSFET击穿特性的影响。以 Si面为例 ,分析了温度对器件的击穿电压、临界电场、比导通电阻等物理量的影响。根据 6H-Si C各向异性的特性 ,采用张量扩展将其扩展到 C面 ,研究表明虽然在不同的晶面上器件的击穿电压不同 ,但其随温度的变化趋势是相同的 ,都具有正温度系数。     

杂质不完全离化对SiC MOSFET的影响

在分析SiC中杂质部分离化时,考虑了Frenkel-Pool效应,通过求解SiC MOS表面空间电荷区中的一维Poisson方程,提出了一个新的SiC MOSFET反型层薄层电荷(charge-sheet)数值模型.对SiC中杂质不完全离化的研究表明,杂质原子较大的离化能、高的掺杂浓度以及低温会使不完全离化的影响增强,对于SiC MOSFET,杂质不完全离化的影响主要在亚阈区.     

杂质不完全离化对SiC MOSFET的影响

在分析 Si C中杂质部分离化时 ,考虑了 Frenkel- Pool效应 ,通过求解 Si C MOS表面空间电荷区中的一维Poisson方程 ,提出了一个新的 Si C MOSFET反型层薄层电荷 (charge- sheet)数值模型 .对 Si C中杂质不完全离化的研究表明 ,杂质原子较大的离化能、高的掺杂浓度以及低温会使不完全离化的影响增强 ,对于 Si C MOSFET,杂质不完全离化的影响主要在亚阈区     

6H-SiC异质结源漏MOSFET的模拟仿真研究

给出了一种新型SiC MOSFET-6H-SiC异质结源漏MOSFET。这种器件结构制备工艺简单,避免了长期困扰常规SiC MOSFET的离子注入工艺难度大、退火温度高等问题,而且具有性能优良,开态电流大,侧墙工艺简单的特点。文中分析了该器件的电流输运机制,并通过器件仿真软件ISE TCAD模拟,给出了SiC异质结源漏MOSFET伏安特性以及其和相关器件结构和工艺参数的关系。     

A novel 6H-SiC power DMOSFET with implanted p-well spacer

In this letter, we utilize a lower thermal budget with an aluminum doped p-well to minimize the effect of “step bunching” and a new structural design with deep spacer implants to prevent the JFET “pinching” action at small p-well spacings (5 μm) in planar vertical double implanted MOSFET (DIMOS) devices fabricated on 6H-SiC. A specific ON-resistance of 42 mΩ-cm² (further reducible by 35% through simple design modification), which represents a 100% reduction over devices which did not receive the spacer implants, is observed on the 2-μm channel devices. This novel scheme will allow increased packing densities for high power applications using the DIMOS structure in SiC     

4H-SiC台阶型沟槽MOSFET器件

介绍了一种4H-SiC台阶型沟槽MOSFET器件.该结构引入了台阶状沟槽,使用TCAD软件对台阶状沟槽的数量、深度、宽度等参数进行了拉偏仿真,确定了最优台阶结构参数.仿真结果表明,与传统的UMOS器件相比,最优台阶结构参数下的台阶状沟槽MOSFET器件关断状态下的栅氧化层尖峰电场减小了12％,FOM值提升了5.1％.提...     

Rapid thermal annealing of ion implanted 6H-SiC by microwave processing

Rapid thermal processing utilizing microwave energy has been used to anneal N, P, and Al ion-implanted 6H-SiC. The microwaves raise the temperature of the sample at a rate of 200°C/min vs 10°C/min for conventional ceramic furnace annealing. Samples were annealed in the temperature range of 1400-1700°C for 2-10 min. The implanted/annealed samples were characterized using van der Pauw Hall, Rutherford backscattering, and secondary ion mass spectrometry. For a given annealing temperature, the characteristics of the microwave-annealed material are similar to those of conventional furnace anneals despite the difference in cycle time.     

存在界面陷阱的n沟6H-SiC MOSFET温度特性研究

利用二维器件仿真软件 MEDICI建立了具有指数分布界面陷阱的 n沟 6H-Si C场效应晶体管的结构模型和物理模型 ,通过模拟研究 ,分析和讨论了界面陷阱对器件阈值电压、跨导及其温度特性的影响。     

6H-SiC埋沟MOSFET的C-V解析模型研究

研究了6H-SiC埋沟MOSFET器件的电容-电压特性,建立了解析模型.具体分析了埋沟MOSFET各种工作模式下的电容与栅电压之间的关系,考虑了SiO2/SiC界面态及pn结对电容-电压特性的影响.对模型进行了仿真分析验证,结果表明:在假设界面态密度分布均匀条件下,由于对界面态做了简化处理,因而在耗尽模式及夹断模式下的C-V特性计算结果与实验结果有所差异.     

增强型4H-SiC埋沟MOSFET的工作机理

本文对一种新型增强型4H-SiC埋沟MOSFET结构的工作机理进行了研究.通过对不同偏压下电荷分布和电势分布的分析,分别总结了线性区和饱和区所包含的工作模式.     

Planar, ion implanted, high voltage 6H-SiC P-N junction diodes

Planar, high voltage (800 V) P-N junction diodes have been fabricated for the first time on N-type 6H-SiC by room temperature boron implantation through a pad oxide deposited within windows etched in an LPCVD field oxide. All the diodes showed excellent rectification with leakage currents of less than 10 nA (~5×10^-5 A/cm² ) until avalanche breakdown. It was found that the breakdown voltage increases with junction depth. The reverse recovery time (t_rr) was measured to be 50 ns for the 800 V diode from which an effective minority carrier life time of 12.5 ns was extracted     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

150V/200V MOSFET

据《世界电子元器件》2009年9月月刊报道,IR推出一系列150 V和200 VHEXFET功率MOSFET,为开关模式电源(SMPS)、不断电系统(UPS)、反相器和DC马达驱动器等工业应用提供极低的闸电荷(Qg)。随着DC/DC功率转换应用技术的日益进步,开关频率也有所提高,输入电     

High-Power 4H-SiC MOSFET with an Epitaxial Buried Channel

Semiconductors - A method for reducing the on-state resistance of a high-power 4H-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) by forming a buried channel via the growth of...     

An 1800 V 300 A nondestructive tester for bipolar power transistors

A nondestructive reverse-bias safe operating area (RBSOA) tester using an ultra-fast shunt circuit is constructed and demonstrated up to an 1800 V 300 A level. An innovative MOSFET shunt circuit is the key to the high power capability of the tester. The tester is an upgraded version of the old tester (rated at 1000 V 120 A) reported by the authors in 1985. The basic operation of the tester is reviewed, the design and the fabrication of the new tester are described, and test results are provided     

2700V4H-SiC结势垒肖特基二极管

在76.2 mm 4H-SiC晶圆上采用厚外延技术和器件制作工艺研制的结势垒肖特基二极管(JBS).在室温下,器件反向耐压达到2700 V.正向开启电压为0.8V,在VF=2V时正向电流密度122 A/cm2,比导通电阻Ron=8.8 mΩ·cm2.得到肖特基接触势垒qφв=1.24 eV,理想因子n=1.