Ultra sharp crystalline silicon tip array used as field emitter

This article describes the fabrication of single crystal silicon field emission tip arrays. Each array consists of 2500 tips. We used 4 in. (100) oriented n type silicon wafers 0.008 – 0.020 Ωcm, Sb doped. The tips were formed using a RIE process. We achieved crystalline emitter tip radiuses of 1.5 – 2 nm. The extraction grid is a self aligned, sputter deposited Ti_0.1W_0.9 film. The radiuses of the extraction grid apertures range from 300 to 150 nm and have a tip to tip spacing from 10 to 5 μm. The testing was done in vacuum with a distance of 500 μm between extraction grid and anode. We have seen maximum stable array currents up to 2 μA. An anode current of 10 nA was initially detected at a minimal gate bias of about 14 V.     

A new fabrication process of field emitter arrays with submicrongate apertures using local oxidation of silicon

The field emitter arrays with submicron gate apertures for low voltage operation have been successfully fabricated by modifying the conventional Spindt process. The key element of the new process is forming the gate insulator by local oxidation of silicon, resulting in the reduction of the gate hole size due to the lateral encroachment of oxide. The gate hole diameter of 0.55 μm has been obtained from the original mask pattern size of 1.55 μm. An anode current of 0.1 μA per emitter is measured at the gate voltage of about 53 V, while the gate current is less than 0.3% of the anode current. To obtain the same current level from a Spindt-type emitter with the same gate hole diameter as the mask pattern size, a gate bias of about 82 V is needed     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

A monolithic field emitter array with a JFET

This paper proposes a novel structure of the conical Si field emitters monolithically incorporating a vertical-type junction field effect transistor (JFET) and demonstrates the emission control in field emission from the emitters. The proposal has many attractive advantages in the display application and reliable fabrication, because the structure needs neither additional area for the JFET nor additional process except ion implantation. The experimental results of the emitters show excellent controllability and stability in the emission current     

A novel structure of silicon field emission cathode with sputteredTiW for gate electrode and TEOS oxide for gate dielectric

A novel silicon field emission cathode structure with a narrow spacing between tip and gate electrode is proposed, based on the filling characteristics of the sputtered Ti_0.1W_0.9 beneath the disc-shaped tip-mask oxide. Without advanced lithography technologies, the hole diameter of the gate is reduced to a sub-half-micrometer of ~0.4 μm from an initial tip-mask size of ~1.2 μm, and the gate electrode easily approaches the cathode, leading to a low-voltage operation. A uniform and stable field emission cathode is obtained using well-established VLSI process technologies. The current-voltage (I-V) characteristics of the cathodes show low turn-on voltages of ~30 V     

A novel gate insulator for flexible electronics

Field effect transistors using a poly(triaryl amine) p-channel organic semiconductor in conjunction with anodised aluminium oxide as the gate insulator (Al₂O₃ on Al) are demonstrated. Anodised films are pinhole-free, homogenous oxide layers of precisely controlled thickness. The anodisation process requires no vacuum steps; anodised Al₂O₃ is insoluble in organic solvents, and Al films are cheaply available as laminates on flexible substrates. Anodised Al₂O₃ is confirmed to have high gate capacitance (≈60 nF/cm²) and electric breakdown strength (>3 MV/cm in the working device). This property profile answers to the demands on gate insulators for flexible electronics applications.     

Anodic oxide film as gate insulator for InP MOSFETs

An anodic oxide film of InP, which had an interface state density of ? 1011 cm?2 eV?1 near midgap and worked well as the gate insulator for InP MOSFETs, was obtained by optimising its preparation conditions. The excellence of the anodic oxide as a gate insulator was confirmed by a high electron effective mobility (1500 cm2/Vs) in the accumulation-mode InP MOSFETs.     

A novel self-aligned T-shaped gate process for deep submicron SiMOSFET's fabrication

T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure     

MOS device fabrication using sputter-deposited gate oxide and polycrystalline silicon layers

For applications in the MOS device fabrication the interface properties of sputtered SiO₂ and SiO₂-polycrystalline silicon layers on silicon substrates were investigated and improved to a quality which is equivalent to those of thermally grown SiO₂ with pyrolytical polycrystalline silicon (polySi). For testing these layers as gate oxide and Si electrodes of MOS transistors the well known Si gate process was varied to include sputter deposition and the optimal deposition, annealing and diffusion parameters were integrated.MOS transistors with sputtered SiO₂ and Si gate material layers and for comparison Al gate devices with sputtered SiO₂ have been fabricated and their threshold voltage behavior was tested.     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

Simulation and design of field emitter array

Some simulation results about potential, field strength, and emitting current density of cone-shaped emitter arrays are presented. Several important design features about the field emitter array are discussed. The most striking feature is that if one wants to obtain more current from the field emitter array in a given device area, there is a limit to the density of the emitter array due to the emitter tip field strength lowering effect, which is a result of the interaction from nearby surrounding tips. If one reduces the tip radius to increase the field strength a higher current density is compensated by a reduced effective emitting area; therefore, to obtain the highest emitter current for a certain set of designed emitter array geometric parameters a corresponding optimal tip radius needs to be determined     

A novel self-aligned fabrication process for microwave static induction transistors in silicon carbide

A novel multiple-self-aligned fabrication process is developed for recessed gate microwave static induction transistors (SITs) in silicon carbide (SiC). This process is demonstrated by fabricating 4H-SiC SITs having record f/sub T/ of 7 GHz.     

Computer simulation of an oxide walled emitter STL gate

A Schottky transistor logic (STL) gate is studied using computer simulation. The relation between propagation delay time and the spacing between the diffused emitter and the isolation oxide is shown to be such that an optimum spacing exists.     

Improved enhancement/depletion GaAs MOSFET using anodic oxide as the gate insulator

A GaAs MOSFET with a semi-insulating substrate is described, operating in either the enhancement or the deed depletion modes and showing the highest transconductance reported so far, and a rise time better than 1 ns. The behavior is fully explained by theC/Vcharacteristics of equivalent MOS capacitors.     

A high-yield fabrication process for silicon neural probes

There is a great need for silicon microelectrodes that can simultaneously monitor the activity of many neurons in the brain. However, one of the existing processes for fabricating silicon microelectrodes-reactive-ion etching in combination with anisotropic KOH etching-breaks down at the wet-etching step for device release. Here we describe a modified wet-etching sidewall-protection technique for the high-yield fabrication of well-defined silicon probe structures, using a Teflon shield and low-pressure chemical vapor deposition (LPCVD) silicon nitride. In the proposed method, a micro-tab holds each individual probe to the central scaffold, allowing uniform anisotropic KOH etching. Using this approach, we obtained a well-defined probe structure without device loss during the wet-etching process. This simple method yielded more accurate fabrication and an improved mechanical profile.     

Solution-processed natural gelatin was used as a gate dielectric for the fabrication of oxide field-effect transistors

Biocompatible and biodegradable materials are attractive for environmentally safe, flexible and biosustainable devices since they are nontoxic renewable materials with a low cost. Gelatin, a natural protein, is a promising biopolymer for photography, cosmetic manufacturing and food. In this paper, solution-processed natural gelatin was used as a gate dielectric for the fabrication of oxide field-effect transistors (FETs). Similarly to a polyelectrolyte, mobile ions can be generated in gelatin in air environment. A high gate specific capacitance larger than 0.93 μF/cm² was obtained in gelatin processed at low concentrations, due to the formation of electric-double-layers (EDLs). As gelatin films processed at a low concentration of 0.02 g/mL, the fabricated FETs showed excellent electrical performances. The average current on/off ratio and the mobility were estimated to be 1.36 × 10⁵ and 33.2 cm²/V, respectively. The proposed technique may be application in the bioelectronics field, including biosensors and synaptic devices.     

A novel approach to silicon gate CMOS device scaling

A new approach is reported for fabricating scaled Si-gate CMOS devices using medium temperature (?900° C) LPCVD deposited SiO₂ as the dielectric interlayer. The film can be deposited from 850 to 1000°C using a graded temperature profile and optimum pressure. A maximum of 100 wafers with 8% variation of thickness per run has been achieved using the process described in this paper. The medium-temperature LPCVD SiO₂ film exhibited step-coverage as good as the conventional low temperature PSG film. Since the new film requires no high temperature treatment, the convetional Si-gate CMOS diffusion process has been used to obtain the micron and submicron junction depths that are required to fabricate scaled CMOS devices. Such a processing approach, converting a 5–6 μm geometry CMOS process to a 3 μm geometry CMOS process, is described.     

A formation of cobalt silicide on silicon field emitter arrays byelectrical stress

A novel process utilizing electrical stress is proposed for the formation of Co silicide on single crystal silicon (c-Si) FEAs to improve the field emission characteristics. Co silicide FEAs formed by electrical stress (ES) exhibited a significant improvement in turn-on voltage and emission current compared with c-Si FEAs. The improvement mainly comes from the lower effective work function of Co silicide and less blunting of tips during silicidation by electrical stress in an ultra high vacuum (UHV) environment less than 10^-8 torr     

High performance low temperature polysilicon thin film transistorusing ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (⩽600°C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm²/V·s for n-channel and 69 (48) cm²/V·s for p-channel respectively when using Si₂ H₆(SiH₄) source gas for the deposition of active poly-Si films     

A novel self-aligned gate process for half-micrometer gate GaAs ICsusing ECR-CVD

A substitutional self-aligned gate MESFET process for the half-micrometer gate GaAs IC that employs techniques of sidewall formation and precise pattern reversal using ECR (electron cyclotron resonance) CVD (chemical vapor deposition) is discussed. A FET with 0.45-μm gate length showed high performance characteristics, such as a maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz. This process has two advantages over conventional substitutional and refractory gate processes. First, it can incorporate an LDD (lightly doped drain) structure. Second, since the photoresist dummy gates are precisely reversed without using reactive ion etching (RIE) at all, the gate length is dependent only on lithography. The process was demonstrated by the preliminary fabrication of a 16 b×16 b multiplier with 50% yield. The process, with high-performance device characteristics, should fine broad applications in both half-micrometer gate level LSIs and analog ICs